Input stage mess
Fred Bartoli
200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to 1MHz.
Lots of interesting pbs to solve. One remaining thing is some stability
issue wrt to cable/generator impedance.
The input stage will be 4 to 6 paralleled Interfet's IF3602. They'll work at
a low servoed 1V VDS to minimze thermal noise problems.
Under those bias condition the JFet will show about 300pF Cgs and 180pF Cgd.
The Jfet is servo-cascoded so that amounts to and equivalent 480pF Cgs.
The closed loop preamplifier show an input impedance that has a painfull
negative real part input admittance.
Admitting a first order response, the input admittance is:
Cgs w^2
Yin = -------------- with WT = 2 pi GBW and beta= feedback network
attenuation
WT beta + j w
This translate to an equivalent parallel network:
2 2 WT beta
Rin(w) = - ------------ - ------------
Cgs WT beta Cgs w^2
1 Cgs w^2
Cin(w) = --- . -------------------
2 w^2 + WT^2 beta^2
Now the figures:
designing for a 10 loop gain (WT beta) at 1MHz this give a low -12R for the
real part at high frequencies and will give a nice oscillation with the
input cable impedance (estimated between 300nH & 500nH).
As the generator impedance is low, the easy way to deal with this could be a
serie RC in parallel with the input (sort of 2-5 nF and under 12R resistor).
Unfortunatly a 10R resistor is 410pV/rtHz and 41pA/rtHz which translates to
about 130pV/rtHz across the 0.5uH cable inductance at 1MHz. A bit more than
I would like.
More, this 10R is dangerously close to the -12R value, which didn't
accounted for additionnal parasitic poles and will probably be lower.
Plus cable resonance with the input capacitance will rise the noise level.
I can't insert a damping resistor in series with the gate connexion for
noise reasons (200pV/rtHz is a super low 2.5R noise resistance).
I've thought of a lot of schemes for neutralizing Cgs, but found nothing
practical.
I also can't run the input stage open loop, which would solve this issue but
will raise some others.
Any idea?
--
Thanks,
Fred.
John Larkin
Can you post a schematic, real or simplified?
John
Mark
I don't undestand why your cable looks inductave anyway?
Is the source Z of the generator equal to the characteristic Z of the
cable?
The only way for the cable to look inductave is for it to be short
length (probably true) and for the generator source Z to be lower then
the cable characteristic Z.
Is the cable charateristic Z 50 Ohms? Whats the generator, a low Z
mic...is this for audio? Why go to 1 MHz?
Mark
Fred Bartoli
message de news:if6no15anrrnfa2r9...@4ax.com...
Here it is.
85mA 85mA
to to
125mA 125mA
V V
| |
+------------------------+--------.
| | | |
.--+ .--+-----+--------. | |
| .-.R3 | .-.R4 | /| | | |\ |
---| | ---| | >| /-|-' '-|-\ |<
---| | ---| | |-< | | >-|
| '-' | '-' /| \+|--+--|+/ |\
'--+ '--+ | \| | |/ |
| | | 2 V |
clamp --. | .-------------------' |
| | | | | | ___
| | | | | .---------------------|___|-.
10u | J1 |-+ | +-|J2 | | | R2 |
|| | | | | | | ___ | |\ |
in -+--||--+--->|-+ | +-|<-------+-|___|-. | .----|+\ |
| || | | | | |5mA R1 | 5mA| | | >-+-out
.-. .-. '---+---' | | GND | | GND .-|-/ |
| | | | | | V V | | |/ |
| | | | | .-----------------------. | |
1M'-' '-'1G | | Precision |--+--||--+
| | V | current mirror | .-.
GND | 160mA '-----------------------' | |
| to /| | |
| 240mA /+|-GND'-'
'------------------------------------------+-< | |
| \-|-+---'
| \| |
'-||---'
J1 and J2 are 4 to 6 paralleled IF3602, no source degeneration (noise),
running at 20mA/transistor.
R3 and R4 are one per transistor and 50R (1V across the Jfet, 1V across the
R)
The feedback path has _low_ impedance (1 fb path per jfet, 1R/27R).
As you can see, nothing terribly fancy. All lies in the details (like the
subject of this post).
For the problem of interest here, it comes from the differential input
voltage which rises 6dB/oct with a 90° shift wrt to the input voltage (due
to the open loop gain pole) and the JFETs capacitances across the inputs
(1.45nF between the preamp in+ and in-) which introduces another 90° shift
for the current injected at J1 gate, hence the negative resistance.
Exactly the same pb as an emitter follower loaded with a cap.
--
Thanks,
Fred.
Phil Hobbs
>
> For the problem of interest here, it comes from the differential input
> voltage which rises 6dB/oct with a 90° shift wrt to the input voltage (due
> to the open loop gain pole) and the JFETs capacitances across the inputs
> (1.45nF between the preamp in+ and in-) which introduces another 90° shift
> for the current injected at J1 gate, hence the negative resistance.
> Exactly the same pb as an emitter follower loaded with a cap.
>
>
Hmm. Looks like the origin of the problem is the overall feedback. Do
you really need the virtual ground? If not, how about making the input
stage a feedforward 20-dB stage instead, and adding the feedback amp
afterwards?
Since your JFETs will be reasonably linear at that I_D, the feedforward
path will have low gain, and hence you can use a higher-noise amp to
generate it. This of course will require a bit of tweaking.
BTW are the 10-uf capacitor leakage and gate current really low enough
to use a gigaohm gate leak resistor-- 1pA ==> 1 mV? And do you really
want a 3 hour time constant on your bias circuit? Oh, and you have two
nearly perfect integrators in your dc feedback loop, which will cause
nasty behaviour.
Cheers,
Phil Hobbs
Frank Miles
Fred Bartoli <fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
[snip]
>> >Well, I've finally got doing that low noise preamp: the target is
>> >200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to 1MHz.
[snip]
Challenging!
I don't know if you can meet the noise specs by going down this pathway,
but if the series RC shunting the input adds too much noise, I think you're
going to have to bootstrap your input circuit to get rid of the negative RC
Zin. This will have to operate at high speed -- not at the slow speed of
the feedback loop. Of course there are limits to this approach as well, but
with the right topology you may be able to use a pure capacitance between J1's
gate and an appropriate virtual ground input node to provide a high frequency
boost to J1's source. This has been done, for example, in a few oscilloscope
vertical inputs to provide a wider-band input while reducing the dribble-up
behavior of real follower circuits which have capacitive loading.
Did you say anywhere what the spec had to be for input capacitance? Perhaps
a bit more HF energy can be stolen from the input? Some other games might
be played if that is allowed. From your resistor values it looks as though
Rin must be high.
Unfortuantely I don't see any way to use the capacitive feed-beside method with
your existing topology. It really needs a follower initial input stage.
This fixes your Zin problem but reaching your noise target will be fun.
I confess I haven't gone through the numbers to determine whether that is
possible with such a different structure. Good luck!
-frank
--
John Larkin
Why is the input stage differential? Seems to me that doing that
increases the noise by 1.41 or something. And all those current
sources look complex and potentially noisy to me.
What are you using for the clamp? I have a similar problem... I need a
pA leakage clamp that can swallow some 10s of mA overloads.
John
Fred Bartoli
Comments inserted below.
"Phil Hobbs" <pcdhSpamM...@electrooptical.net> a écrit dans le
message de news:438C7D09...@electrooptical.net...
> Fred Bartoli wrote:
>
> >
> > For the problem of interest here, it comes from the differential input
> > voltage which rises 6dB/oct with a 90° shift wrt to the input voltage
(due
> > to the open loop gain pole) and the JFETs capacitances across the inputs
> > (1.45nF between the preamp in+ and in-) which introduces another 90°
shift
> > for the current injected at J1 gate, hence the negative resistance.
> > Exactly the same pb as an emitter follower loaded with a cap.
> >
> >
>
> Hmm. Looks like the origin of the problem is the overall feedback.
Yes.
> Do you really need the virtual ground?
Which virtual ground are you speaking about? The whole preamplifier is
non-inverting.
> If not, how about making the input
> stage a feedforward 20-dB stage instead, and adding the feedback amp
> afterwards?
>
> Since your JFETs will be reasonably linear at that I_D, the feedforward
> path will have low gain, and hence you can use a higher-noise amp to
> generate it. This of course will require a bit of tweaking.
>
Hmmm, feedforward is one thing I forgot to think about. I can smell some
interesting idea here but right now I fail to see exactly what you have in
mind. Can you sketch something?
One thing I can't do is getting the Jfets out of the feedback loop. The
preamplifier will have 2 purposes:
1) investigate noise in a _very_ low noise power supply (200nV rms)
2) measure the supply transient recovery to an injected charge. The measured
recovery is about 200nV, so expected aberrations (electric and thermal)
should be lower than 50nV,... excluding noise :-)
Unfortunatly the initial transient can be a few 100mV, up to about half a
volt, and will induce nasty thermal tails if the jfets were working open
loop.
Working with an hypothesis of 1mV/K offset gives 50uK for the stability, and
200pV/rtHz translates to 0.2uK/rtHz, so some serious power stabilisation is
in order there.
> BTW are the 10-uf capacitor leakage and gate current really low enough
> to use a gigaohm gate leak resistor-- 1pA ==> 1 mV?
I've measured some of the Jfets at under 2pA gate leakage under these
conditions, much better than the given specs and this is for a few boxes, so
that's OK for me. I was pleasently surprised because these are pretty big
transistors and this will simplify my already enough complicated life.
The 10uF are specified at 25000s minimum time constant, i.e. 2.5 gigaohm.
The input DC component is about 10V and I've again measured some samples
much better. Again I can select so it's OK too.
And do you really
> want a 3 hour time constant on your bias circuit?
An unfortunate side effect of the low frequency requirements.
I've not shown some speed up circuitry which was not relevant to the pb.
The 10uF is mandatory because of the gate shot noise rising the input noise
at low frequency, and the bias resistor has to be 1Gohm because I obviously
don't want its current noise be greater than the gate noise current.
> Oh, and you have two
> nearly perfect integrators in your dc feedback loop, which will cause
> nasty behaviour.
>
Oops, yes I obviously missed a zero somewhere :-)
--
Thanks,
Fred.
John Popelish
Perhaps a resistor in series with the output opamp feedback capacitor
could cancel one of those poles.
Fred Bartoli
"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> a écrit dans le
Yep. It indeed increases noise by a sqrt(2) factor and makes me double the
Fets number to regain it... and worsens the negative resistance number by
the same factor as a side effect :-)
Anyway some other problems make this a preferred solution:
A single branch input stage will have to either have its source current
provided by the feed back network (if one use feedback around it), or
compensated with a current source.
The preamplifier will have 2 purposes (and 2 modes):
1) investigate noise in a _very_ low noise power supply (200nV rms). In this
mode the diff input stages provide good rejection of the common tail current
source variations. With a single sided input stage this noise will not be
reduced.
2) measure the supply transient recovery to an injected charge. The measured
recovery is about 200nV, so expected aberrations (electric and thermal)
should be lower than 50nV,... excluding noise :-)
Unfortunatly the initial transient can be a few 100mV, up to about half a
volt. I obviously can't have the lower feedback resistor (0.2R!) stand half
a volt (and I want the power to be limited: low noise switching supply for
the isolated input stages, low thermal convection noise and blah...), so in
this mode, where I can average out the noise, the feedback network is
switched to a more current friendly 100R/2.7K per transistor, which will
represent a manageable total 20-30mA at 0.5V input.
This feedback network obviously can't provide the 100mA transistor current,
so a compensation current source would be required, with a too big impact on
LF noise.
Another pb for the single sided solution is that the source will have to be
servoed at 0V (current in the 0.2R fb resistor) which will make the gate
potential between -0.1/-0.5V, with potential leakage problems in the
protection device.
A few mV is all I can accept here.
Yet another pb is the looong input time constant and the diff input stage
will help slow thermal drift rejection.
And... and...
> What are you using for the clamp? I have a similar problem... I need a
> pA leakage clamp that can swallow some 10s of mA overloads.
>
Probably something like this. As I can't have any series resistance, at
least at the begining of an input event, the diodes will have to cope with
high current pulses.
----+--+--------+------
| | |
V - |
- ^ |
| | /| |
| | /+|-'
+--+---< |
| | \-|-.
| | \| |
| +--------+-----> current limiting switch command
| |
V -
- ^
| |
GND GND
And also probably some switched current limiting resistor (I can have a
permanent one due the noise specs), because I have to protect the supply
under test from the 10uF cap charge (and discharge).
Unless I discover the miraculous depletion transistor with ultra high Gfs
and low Idss.
Maybe I can have my little daughter write this down on her letter to SK, but
I guess she'll fell upset if I have that nice transistor and something else
is missing.
Do you know such a beast? :-)
Hmmm, the IF3601-02 I have measure 1.9ohm RDSon. Maybe I should look a bit
further, but not too much hope...
--
Thanks,
Fred.
John Larkin
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
>
>One thing I can't do is getting the Jfets out of the feedback loop. The
>preamplifier will have 2 purposes:
>1) investigate noise in a _very_ low noise power supply (200nV rms)
>2) measure the supply transient recovery to an injected charge. The measured
>recovery is about 200nV, so expected aberrations (electric and thermal)
>should be lower than 50nV,... excluding noise :-)
>Unfortunatly the initial transient can be a few 100mV, up to about half a
>volt, and will induce nasty thermal tails if the jfets were working open
>loop.
>Working with an hypothesis of 1mV/K offset gives 50uK for the stability, and
>200pV/rtHz translates to 0.2uK/rtHz, so some serious power stabilisation is
>in order there.
>
How about a transformer?
http://www.thinksrs.com/products/SR554.htm
John
Fred Bartoli
"John Popelish" <jpop...@rica.net> a écrit dans le message de
news:zeGdnY7c6c_xWRHe...@adelphia.com...
Fred Bartoli wrote:
I don't know why but some messages I answer are not quoted so I have to
manually add the quote sign, like below, to keep the message understandable.
Anybody knows why?
>Perhaps a resistor in series with the output opamp feedback capacitor
>could cancel one of those poles.
I've first thought of this, but this is just pushing up the GBW product and
when the loop gain falls again, guess what...
On the same note I've thought of limiting the gain in the pass band to have
it uniform, like loopgain = constant (50) from LF to the corner freq. But
the outcome is the same at HF.
--
Thanks,
Fred.
John Popelish
>>Perhaps a resistor in series with the output opamp feedback capacitor
>>could cancel one of those poles.
>
>
> I've first thought of this, but this is just pushing up the GBW product and
> when the loop gain falls again, guess what...
> On the same note I've thought of limiting the gain in the pass band to have
> it uniform, like loopgain = constant (50) from LF to the corner freq. But
> the outcome is the same at HF.
So where are the natural poles in this circuit, not counting the one
at zero for the output integrator? I would put the zero at the lowest
one of these poles. Setting this feedback zero would also probably
include increasing the size of the integrator capacitor, to reduce the
low frequency gain so that the second pole occurs beyond unity gain.
Fred Bartoli
"Frank Miles" <f...@u.washington.edu> a écrit dans le message de
news:dmi624$fs0$1...@gnus01.u.washington.edu...
Yup. From the whole bunch of pb I could list I'm pretty safe to say that
this is probably the limit of what's doable at room temperature.
> I don't know if you can meet the noise specs by going down this pathway,
> but if the series RC shunting the input adds too much noise, I think
you're
> going to have to bootstrap your input circuit to get rid of the negative
RC
> Zin. This will have to operate at high speed -- not at the slow speed of
> the feedback loop. Of course there are limits to this approach as well,
but
> with the right topology you may be able to use a pure capacitance between
J1's
> gate and an appropriate virtual ground input node to provide a high
frequency
> boost to J1's source. This has been done, for example, in a few
oscilloscope
> vertical inputs to provide a wider-band input while reducing the
dribble-up
> behavior of real follower circuits which have capacitive loading.
>
Hmmm, now that sounds interesting. That really is a clever trick, if I
understood correctly what you meant.
Do you have any specific scope reference or schematics to look at?
Plus, in my case, the following current mirror and summing, neutralize this
current injection (from the loop gain POV).
Really nice!
> Did you say anywhere what the spec had to be for input capacitance?
Perhaps
> a bit more HF energy can be stolen from the input? Some other games might
> be played if that is allowed. From your resistor values it looks as
though
> Rin must be high.
>
Not at all (well in AC). The source is low impedance (indeed, it is a low
noise one).
The (almost only) limiting factor is the cable series inductance, up to 1
meter length requested, but I hope I can cut this by half.
What other nice thing do you have in mind? I've made me curious :-)
For the high value resistors, as I explained in my answer to Phil Hobbs, the
1G is there to achieve the specs at the low frequency end.
The 1M at input is here because I expect to use its noise to check the
connected-unconnected state and it is also a weak pulldown for the DC
blocking cap. I also don't want current induced contact noise, so I reduce
it to the minimum level.
> Unfortuantely I don't see any way to use the capacitive feed-beside method
with
> your existing topology. It really needs a follower initial input stage.
>
Maybe I can see some solutions.
> This fixes your Zin problem but reaching your noise target will be fun.
> I confess I haven't gone through the numbers to determine whether that is
> possible with such a different structure. Good luck!
>
Time to check...
--
Thanks,
Fred.
Phil Hobbs
>
> One thing I can't do is getting the Jfets out of the feedback loop. The
> preamplifier will have 2 purposes:
> 1) investigate noise in a _very_ low noise power supply (200nV rms)
> 2) measure the supply transient recovery to an injected charge. The measured
> recovery is about 200nV, so expected aberrations (electric and thermal)
> should be lower than 50nV,... excluding noise :-)
> Unfortunatly the initial transient can be a few 100mV, up to about half a
> volt, and will induce nasty thermal tails if the jfets were working open
> loop.
> Working with an hypothesis of 1mV/K offset gives 50uK for the stability, and
> 200pV/rtHz translates to 0.2uK/rtHz, so some serious power stabilisation is
> in order there.
>
Well, your amp is going to take a long time to stabilize when you turn
it on, just based on that 10,000 second time constant. With a 15V power
supply, the bias loop will slew at (at most) 15 mV/s.
If all you want is a noise measurement, you can use the correlation
trick: put two amplifiers on it, and cross-correlate their outputs. The
amplifier noise goes away and the true signal survives. Gives you a
nice mean-square noise measurement. You can set the measurement
bandwidth and integration time separately to get the measurement you
need--e.g. you can measure the noise in 1 MHz bandwidth but integrate
for 1 second, and get a 60 dB noise improvement.
You can get rid of the thermal tails pretty well by biasing the JFETs at
their peak power points.
Alternatively, you might consider turning the problem inside out: use a
normal op amp to do most of the job and use the JFETs to measure its
differential input voltage, so that the *JFETs* are the feedforward
path. If you can match the gains of two signal paths accurately, you
can get the low noise of the JFETs and the stability of a normal op amp.
The noise suppression you can get with that trick will be limited by the
gain matching and phase shift between the JFET feedforward path and the
normal op amp path.
(Anybody done that before? I might have invented it just now.)
Cheers,
Phil Hobbs
Fred Bartoli
"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> a écrit dans le
message de news:5ojpo1h51hvs6idu0...@4ax.com...
I've seen it. Unfortunatly its nasty input impedance, 3R at 1Hz, 0.2R at
0.1Hz, won't fit the bill.
I wish it would. Well, in fact no: No pb, no contract... :-)
--
Thanks,
Fred.
Fred Bartoli
> Fred Bartoli wrote:
>
> >
> > One thing I can't do is getting the Jfets out of the feedback loop. The
> > preamplifier will have 2 purposes:
> > 1) investigate noise in a _very_ low noise power supply (200nV rms)
> > 2) measure the supply transient recovery to an injected charge. The
measured
> > recovery is about 200nV, so expected aberrations (electric and thermal)
> > should be lower than 50nV,... excluding noise :-)
> > Unfortunatly the initial transient can be a few 100mV, up to about half
a
> > volt, and will induce nasty thermal tails if the jfets were working open
> > loop.
> > Working with an hypothesis of 1mV/K offset gives 50uK for the stability,
and
> > 200pV/rtHz translates to 0.2uK/rtHz, so some serious power stabilisation
is
> > in order there.
> >
>
> Well, your amp is going to take a long time to stabilize when you turn
> it on, just based on that 10,000 second time constant. With a 15V power
> supply, the bias loop will slew at (at most) 15 mV/s.
>
I don't remember if I've already said this, but I have a fast settling mode
to keep this time in the seconds area. The only unknown is dielectric
absorption, but a quick check will say all.
> If all you want is a noise measurement, you can use the correlation
> trick: put two amplifiers on it, and cross-correlate their outputs. The
> amplifier noise goes away and the true signal survives. Gives you a
> nice mean-square noise measurement. You can set the measurement
> bandwidth and integration time separately to get the measurement you
> need--e.g. you can measure the noise in 1 MHz bandwidth but integrate
> for 1 second, and get a 60 dB noise improvement.
>
I remember you already mentioned this but we also want the spectral density
repartition in order to be able to diagnose the causes.
> You can get rid of the thermal tails pretty well by biasing the JFETs at
> their peak power points.
>
Already done. I also wish I could bias them at their temperature
compensation point but the high current value render this impractical :-(
> Alternatively, you might consider turning the problem inside out: use a
> normal op amp to do most of the job and use the JFETs to measure its
> differential input voltage, so that the *JFETs* are the feedforward
> path. If you can match the gains of two signal paths accurately, you
> can get the low noise of the JFETs and the stability of a normal op amp.
>
Again I'm not sure I see all the details of what you have in mind. Can you
elaborate?
But wait... Hmmm, you're giving me another idea, or maybe the same, just
pushed a bit further, or presented differently...
If I reduce the overall GBW product I rise the resistance negative part and
also reduce the maximum possible frequency of oscillation, hence increase
cable inductance tolerance (is this enough, I'll have to check this point).
Combined with feedforwarding the JFETs signal we could hold a good starting
solution.
Combining all this with a bandwidth limited (since we have ffwd) version of
the Frank Miles' "source boost" trick to get rid of the last bit of negative
resistance and it could well be a perfect match to what I looked for.
> The noise suppression you can get with that trick will be limited by the
> gain matching and phase shift between the JFET feedforward path and the
> normal op amp path.
>
> (Anybody done that before? I might have invented it just now.)
>
I'll look into all that tomorrow. It's time to bed now.
--
Thanks,
Fred.
Mark
Mark
Fred Bartoli
"Mark" <mako...@yahoo.com> a écrit dans le message de
news:1133321520....@o13g2000cwo.googlegroups.com...
> Why do you need BW to 1 MHz to check a power supply output?
>
> Mark
>
Yes, why...
Well, because... :-)
Seriously, because those power supplies are part of an ultra sensitive high
definition, real time, video imaging system where some minor aspects of
noise have huge impact on the image quality. Spatial and temporal coherency
of noise, as sampled by the imager, is of primary concern and effects well
below an LSB of the 16b ADCs are visible and annoying.
And when the final customer pays $5M for one system he simply wants the very
best quality :-)
--
Thanks,
Fred.
Ken Smith
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
I've done things like that and have a couple of suggestions:
note the points A and B.
>>in -+--||--+--->|-+ | +-|<-------+-|___|-. | .----|+\ |
>> | || | | | | |5mA R1 | 5mA| | | >-+-out
>> .-. .-. '---+---' | | GND | | GND .-|-/ |
>> | | | | | | V V | | |/ |
>> | | | | | .-----------------------. | |
>> 1M'-' '-'1G | | Precision |--+--||--+ <-A
>> | | V | current mirror | .-.
>> GND | 160mA '-----------------------' | |
>> | to /| | |
>> | 240mA /+|-GND'-'
>> '------------------------------------------+-< | |
>> | \-|-+---' <-B
>> | \| |
>> '-||---'
>>
(1)
If you add a switch and to switch in a lower resistance between A and B,
you can get the circuit settled more quickly.
(2)
If you add a series RC from A to B you can add a zero to the bias point
servo. You can use this to get rid of peaking at the gain cross over
point.
--
--
kens...@rahul.net forging knowledge
Fred Bartoli
"Ken Smith" <kens...@green.rahul.net> a écrit dans le message de
news:dmkfp8$52l$1...@blue.rahul.net...
Ken,
the pb here, as noted by Phil, isn't introducing a zero somewhere, which I
stupidly forgot in the ascii art, and finding where to insert it. It's
mainly the 1G resistor that limits the slewing rate to about 15mV/s which
imposes impractical settling times if left as is. So I also have to switch
some "low" value resistor in parallel to the 1G to allow fast settling
times, then once settled, switch in the rigth time constants to obtain the
full specs (and obviously preserve stability). This was purposely omitted in
the ascii art for clarity.
One thing to take care of is the switch leakages (shot noise in the
protection diodes), hopefully not more than 1 or 2 JFETs gate leakage (so
under 4pA) in order to preserve the low low frequency noise.
--
Thanks,
Fred.
Mark
not a requirement
so what you need is a 50 Ohm amplifer with BW from say 10kHz to 1 MHz
with a low noise figure?? They make amplifiers with < 1 dB noise
figure at 1 GHz these days.
So why have the big feedback loop which is creating your instability
problem and cannot help noise figure?
How about a J310 Nch JFET in common gate, really simple and low noise
Also I would think that a passive LC filter would be VERY effective at
reducing the noise out of a power supply in the 1 MHz region...
and if it is a switching supply, I cannot imagine that the random noise
is a bigger problem compared to the switching freq..
if it is a linear PSU , a few sections of passive filter should take
the random noise down to the thermal noise floor..
what am I missing?
Mark
Frank Miles
[snip]
>Yup. From the whole bunch of pb I could list I'm pretty safe to say that
>this is probably the limit of what's doable at room temperature.
>
>
>> I don't know if you can meet the noise specs by going down this pathway,
>> but if the series RC shunting the input adds too much noise, I think
>you're
>> going to have to bootstrap your input circuit to get rid of the negative
>RC
>> Zin. This will have to operate at high speed -- not at the slow speed of
>> the feedback loop. Of course there are limits to this approach as well,
>but
>> with the right topology you may be able to use a pure capacitance between
>J1's
>> gate and an appropriate virtual ground input node to provide a high
>frequency
>> boost to J1's source. This has been done, for example, in a few
>oscilloscope
>> vertical inputs to provide a wider-band input while reducing the
>dribble-up
>> behavior of real follower circuits which have capacitive loading.
>>
>
>Hmmm, now that sounds interesting. That really is a clever trick, if I
>understood correctly what you meant.
>Do you have any specific scope reference or schematics to look at?
The first place I saw this was in an early FET-input oscilloscope probe.
Unfortunately I can't recall the model. The idea is pretty simple, really:
|
|--+
|
in ------------->|--+
| |
| |------ out
| c |
_|_ \ |
___ \|______
| /|
| e </ |
| |
|__________|
| I
The capacitor is sized to steal enough HF energy from the input signal to
drive the next stage's input capacitance. Its inter-lead voltages never
experience any voltage change, so the device's capacitances never experience
any change in charge. Bootstrapping the drain is necessary, of course,
both to keep capacitive currents and thermals from wreaking their havoc.
Not shown, of course, is the input bias circuit. Since you're not interested
in dc this should make some aspects easier -- the bias can be servoed.
The current-source NPN can't be bootstrapped, to preserve the 'virtual ground'
seen by the low side of the input capacitor, but a souped-up variant could
be used in place of a simple/single NPN.
If you really don't need the impedance buffering, however, this may all be
pointless. You may have already tossed this, but perhaps you "only" need
to create a super-low-noise, stable sample-hold device, along with a somewhat
more traditional low-voltage-noise amplifier (with input protection). It
doesn't seem like you need the super-low Iin of the FET, do you? Of course,
such a sample-hold might be harder to build than the amplifier!
Good luck ... HTH...
-frank
--
Fred Bartoli
> ok, so this is not for an audio mic pre....so ultra low distortion is
> not a requirement
>
> so what you need is a 50 Ohm amplifer with BW from say 10kHz to 1 MHz
> with a low noise figure?? They make amplifiers with < 1 dB noise
> figure at 1 GHz these days.
>
Yep, they make this. What I want is 200pV/rtHz (yes that's pV), which is a
2.5R noise resistance.
That translates to under 0.2dB noise figure for a 50R system.
> So why have the big feedback loop which is creating your instability
> problem and cannot help noise figure?
>
> How about a J310 Nch JFET in common gate, really simple and low noise
>
Do the maths, its gfs is a pitiful 17mS typ. Plus the J310 has a huge low
frequency noise, spec'ed at 10nV/rtHz @ 100Hz, missing the target by a 50
factor. Not great and probably much much worse at 1Hz and 0.1Hz.
> Also I would think that a passive LC filter would be VERY effective at
> reducing the noise out of a power supply in the 1 MHz region...
>
No.
> and if it is a switching supply, I cannot imagine that the random noise
> is a bigger problem compared to the switching freq..
>
They are SMPS and are not a pb, but I won't give you all the details.
> if it is a linear PSU , a few sections of passive filter should take
> the random noise down to the thermal noise floor..
>
> what am I missing?
>
The specs. by far, I'm afraid :-)
Now you're welcomed to throw in a few components and submit your solution
here.
Here is the target:
- BW 0.1Hz - 1MHz
- noise floor 200pV/rtHz
- noise density at 0.1Hz not greater than 2nV/rtHz
- must cut the DC input voltage (up to +/- 15V)
- fast settling time (seconds)
- must also withstand 500mV input pulses and be able to characterise a
recovery to 200nV in 50uS
- must be floating
- should be user friendly
Oh, and you deliver it mid february.
--
Thanks,
Fred.
Jim Thompson
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
[snip]
>>
>
>The specs. by far, I'm afraid :-)
>
>Now you're welcomed to throw in a few components and submit your solution
>here.
>Here is the target:
>- BW 0.1Hz - 1MHz
>- noise floor 200pV/rtHz
>- noise density at 0.1Hz not greater than 2nV/rtHz
>- must cut the DC input voltage (up to +/- 15V)
>- fast settling time (seconds)
>- must also withstand 500mV input pulses and be able to characterise a
>recovery to 200nV in 50uS
>- must be floating
>- should be user friendly
>
>Oh, and you deliver it mid february.
Looks like a cakewalk to me ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Fred Bartoli
"Jim Thompson" <To-Email-Use-Th...@My-Web-Site.com> a écrit dans
le message de news:mr2so15j89mtv3jvk...@4ax.com...
> On Wed, 30 Nov 2005 21:27:12 +0100, "Fred Bartoli"
> <fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
>
> [snip]
> >>
> >
> >The specs. by far, I'm afraid :-)
> >
> >Now you're welcomed to throw in a few components and submit your solution
> >here.
> >Here is the target:
> >- BW 0.1Hz - 1MHz
> >- noise floor 200pV/rtHz
> >- noise density at 0.1Hz not greater than 2nV/rtHz
> >- must cut the DC input voltage (up to +/- 15V)
> >- fast settling time (seconds)
> >- must also withstand 500mV input pulses and be able to characterise a
> >recovery to 200nV in 50uS
> >- must be floating
> >- should be user friendly
> >
> >Oh, and you deliver it mid february.
>
> Looks like a cakewalk to me ;-)
>
Nah. You don't know how to design transistors by square meters :-)
--
Thanks,
Fred.
Mark
power supply????
These kind of low noise figures are useful for satellite receivers
where the system noise is below the thermal noise floor of room
temperature since the antennas are pointed out into cold space.
Since the device you are measureing is at room temperature, it is not
logical to think that you need an amplifer with a noise figure better
then say 3 dB. An amplifer with a noise figure of 3 dB , when
connected to a room temperature source, (like yours) will deliver an
output signal S/N that is 3 dB worse compared to using a _perfect
noiseless_ amplifer. This should still be perfectly good for making a
measurment.
One of us does not understand your application,,, I hope it is me.
Have fun...
Mark
Fred Bartoli
I guess so.
> Have fun...
>
Thanks.
--
Thanks,
Fred.
Fred Bartoli
"Fred Bartoli"
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> a écrit dans
le message de news:438cb657$0$21244$626a...@news.free.fr...
> Thanks Phil.
> Comments inserted below.
>
>
> "Phil Hobbs" <pcdhSpamM...@electrooptical.net> a écrit dans le
> message de news:438C7D09...@electrooptical.net...
<snip>
> > BTW are the 10-uf capacitor leakage and gate current really low enough
> > to use a gigaohm gate leak resistor-- 1pA ==> 1 mV?
>
> I've measured some of the Jfets at under 2pA gate leakage under these
> conditions, much better than the given specs and this is for a few boxes,
so
> that's OK for me. I was pleasently surprised because these are pretty big
> transistors and this will simplify my already enough complicated life.
>
> The 10uF are specified at 25000s minimum time constant, i.e. 2.5 gigaohm.
> The input DC component is about 10V and I've again measured some samples
> much better. Again I can select so it's OK too.
>
Have just tested a Philips (now Vishay-BC component) MKP378 2.2uF 250V.
They are amazingly good.
Under 20V bias, they show less than 1pA (probably 0.5pA) leakage.
That's more than 20000 Gohm isolation and an impressive 44.10^6 seconds
(>500days) time constant, for a 10^5 min specified.
I guess they'll be good enough :-)
--
Thanks,
Fred.
Ken Smith
Fred Bartoli <fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
[...]
>stupidly forgot in the ascii art, and finding where to insert it. It's
>mainly the 1G resistor that limits the slewing rate to about 15mV/s which
>imposes impractical settling times if left as is.
You could make the op-amp swing to some outragous voltage like 100V to
speed things up a bit.
>One thing to take care of is the switch leakages (shot noise in the
>protection diodes), hopefully not more than 1 or 2 JFETs gate leakage (so
>under 4pA) in order to preserve the low low frequency noise.
You may be able to make the protection diodes serve double purpose. If
their far ends are hooked to active circuits. you could drive them into
conduction to center the circuit.
Ken Smith
Mark <mako...@yahoo.com> wrote:
>so you think you need an amplifer with a 0.2 dB noise figure to test a
>power supply????
No, he needs an amplifier that has less noise voltage than the supply
does. The resistive component of the impedance at the output of the
supply is very low and hence the thermal noise floor is very low.
Try assuming the impedance of the system is 1 Ohm not the 50 Ohms you
normally think about.
Fred Bartoli
> In article <438dcc16$0$21209$626a...@news.free.fr>,
> Fred Bartoli
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
> [...]
> >stupidly forgot in the ascii art, and finding where to insert it. It's
> >mainly the 1G resistor that limits the slewing rate to about 15mV/s which
> >imposes impractical settling times if left as is.
>
> You could make the op-amp swing to some outragous voltage like 100V to
> speed things up a bit.
>
That'll reduce the settling time from 3 hours to about 20min. Much better
but the requirement is about 1 second (a few seconds at worst).
So will need 100kV with this scheme. Well probably not because when the arc
will trigger the 10u input cap will charge pretty fast :-)
>
> >One thing to take care of is the switch leakages (shot noise in the
> >protection diodes), hopefully not more than 1 or 2 JFETs gate leakage (so
> >under 4pA) in order to preserve the low low frequency noise.
>
> You may be able to make the protection diodes serve double purpose. If
> their far ends are hooked to active circuits. you could drive them into
> conduction to center the circuit.
>
Good idea. It'll require that I push the clamp level to 3 diodes drop
instead of 2 but that's probably OK.
Thanks.
--
Thanks,
Fred.
Mark
OK so the OP is trying to measure a very small voltage signal FROM A
VERY LOW SOURCE Z.
In which case he needs to look at amplifers with very low input noise
voltage but the input noise current is not critical. I think that
leads back to topologies that have a low input Z like common base or
common gate so that they are able to extract the most "power" from the
desired signal. A high Z input to an FET gate is not the correct
approach.
Mark
Fred Bartoli
You're still missing the point. The source is a power supply so I have to
block the DC component with... tadam! a cap which has a rising impedance at
low frequency, so the input current noise is of primary importance too. And
a fet input _is_ the correct approach.
If I had not that pb, the correct approach wouldn't be a discrete input
stage but toss 16 AD797 together and it's done. Unfortunately it isn't.
--
Thanks,
Fred.
Ken Smith
Mark <mako...@yahoo.com> wrote:
[.. 200pV/sqrt(hz) ...]
>In which case he needs to look at amplifers with very low input noise
>voltage but the input noise current is not critical. I think that
>leads back to topologies that have a low input Z like common base or
>common gate
The input noise of a bipolar or FET appears as though it is a small
voltage source in series with the gate or base lead. Changing the
topology to gommon gate/base doesn't change the noise voltage. It just
lowers the power gain.
The OP is basically stuck. There is no way around the need to make the
input devices have a low noise voltage.
Ken Smith
Fred Bartoli <fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
[....]
>If I had not that pb, the correct approach wouldn't be a discrete input
>stage but toss 16 AD797 together and it's done. Unfortunately it isn't.
You could use a couple of hundred TL074 input stages. :)
BTW: You could use a common gate stage if you floated the whole thing at
the average input voltage. Sort of like this:
Input --+------ --------- To more stuff
! ! !
! -----
! ^
! !
-\/\/---+
1G !
--- 1F
---
!
GND
You will notice that I didn't say this was a good idea.
Phil Hobbs
>
> The OP is basically stuck. There is no way around the need to make the
> input devices have a low noise voltage.
Except the correlation method, which only works for rms measurements.
OTOH, it can reach noise levels otherwise unattainable to
room-temperature circuitry.
Cheers,
Phil Hobbs
Ken Smith
I assume in this case you mean:
(1)
Connect two amplifiers to the signal.
(2)
Multiply the outputs of said amplifiers.
(3)
Average the product and then SQRT() to get RMS.
This works ok but it does require longish averaging times if you want to
do a lot better than the amplifiers do on their own.
If you run each amplifier into an ADC and do a bit of math with them, You
can make a bandwidth filtered measurement to get the noise within some
band.
BTW: I've used this with an averaging time equal to one weekend.
Mark
if it is so hard to make this measurment, how is it that the
application circuit (that is being powered by this power supply) is
able to detect this noise so readily?
Mark
Fred Bartoli
Eye seeing an whole region averages a lot of pixels + "contrast zooming" and
some other "small" things.
Having seen it, I can tell you it's absolutly obvious, even to the not
trained eyes, which are certainly not the final users.
--
Thanks,
Fred.
Fred Bartoli
"Ken Smith" <kens...@green.rahul.net> a écrit dans le message de
news:dmo7vt$b6o$2...@blue.rahul.net...
> In article <438f4ee8$0$21221$626a...@news.free.fr>,
> Fred Bartoli
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
> [....]
> >If I had not that pb, the correct approach wouldn't be a discrete input
> >stage but toss 16 AD797 together and it's done. Unfortunately it isn't.
>
> You could use a couple of hundred TL074 input stages. :)
>
He he, 100 x TL74 : say 10pF/opamp and we're back to square one :-)
And it'd be more like 6400 x TL74. Ouch...
> BTW: You could use a common gate stage if you floated the whole thing at
> the average input voltage. Sort of like this:
>
>
> Input --+------ --------- To more stuff
> ! ! !
> ! -----
> ! ^
> ! !
> -\/\/---+
> 1G !
> --- 1F
> ---
> !
> GND
>
> You will notice that I didn't say this was a good idea.
>
Not even. Your noise floor depends on the total gm and you'll need to run a
lot of juice into the fet. The supply can't handle that and if you AC couple
it you'll have to provide a constant current source.
Also note that a BJT is even less an option here because of the emitter shot
noise current:
neglecting Rbb' (which we obviously can't) 200pV/rtHz will call for at least
IC = 2.q.Ut^2/en^2 = 5.4mA
and an input shot noise current being at least sqrt(2.q.IC)=42pA/rtHz, hence
an input DC blocking cap impedance = 2000/42=48 ohm.
For a 2nV/rtHz noise @ 0.1Hz, this is 33000uF which is a pretty big cap,
with its own issues :-)
Good try anyway :-)
--
Thanks,
Fred.
John Devereux
> "Ken Smith" <kens...@green.rahul.net> a écrit dans le message de
> news:dmo7vt$b6o$2...@blue.rahul.net...
> > BTW: You could use a common gate stage if you floated the whole thing at
> > the average input voltage. Sort of like this:
> >
> >
> > Input --+------ --------- To more stuff
> > ! ! !
> > ! -----
> > ! ^
> > ! !
> > -\/\/---+
> > 1G !
> > --- 1F
> > ---
> > !
> > GND
> >
> > You will notice that I didn't say this was a good idea.
> >
>
> Not even. Your noise floor depends on the total gm and you'll need
> to run a lot of juice into the fet. The supply can't handle that and
> if you AC couple it you'll have to provide a constant current
> source.
>
I was thinking of something along the lines of:
___
. +--|___|-+
. | 10 |
. 1 | |
. ___ | |\| |
. +-|___|--+--|-\ |
. ---+ ___ | >--+----
. +-|___|--o--|+/
. 1k | |/| 8 x AD797 etc
. |
. ---
. --- BFC
. |
. ----+-----
But I dont know what the minimum (AC) loading needs to be.
I am trying to leverage the fact that (I assume) you don't need a
high input impedance.
--
John Devereux
Fred Bartoli
"John Devereux" <jdRE...@THISdevereux.me.uk> a écrit dans le message de
news:87d5kfj...@cordelia.devereux.me.uk...
Hi John,
turning your drawing upside down you can see it's exactly the same as the
more usually represented
BFC
|| |\
----||--+-----------|+\
|| | | >--+------
| .-----|-/ |
| | |/ |
| | ___ |
| +----|___|--'
.-. .-. 10
| | | |
1K| | | |1
'-' '-'
| |
--------+-----'
with the opamp supplies common point displaced across the input.
Unfortunatly it will suffer exactly the same shortcomings which are too high
noise current through the blocking cap, huge blocking cap value and *poor*
behaviour of these caps at such a low level, cap charging pb,...
And changing the opamp supply return point, you've just added another pb,
which is a too low input impedance (1R or so) which will make a superbe
voltage divider with the cable inductance, loosing about 10dB of the
precious signal at the upper corner of the bandwidth (0.5uH @ 1MHz = 3R).
The AD797 has also 0.8nV/rtHz noise which calls more for 16 opamps than 8.
--
Thanks,
Fred.
Mark
let me ask a slightly different way...
if it is hard to build a circuit that has sufficently low self noise
comapred to the power supply to make the measurment..
why is it that the application ciruict can have sufficently low self
noise such that the noise from the power supply is the dominnat
problem?
In other words, I don't doubt that your video display or whatever is
very critical and it's easy to see small amounts of noise on the
screen....
but how can this video circuit itself have noise that is so much lower
than the power supply when the power supply noise is so low we can't
measure it.
Mark
John Larkin
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote:
>Well, I've finally got doing that low noise preamp: the target is
>200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to 1MHz.
>
I wonder what the math would be like on a varicap LC oscillator
driving a spectrum analyzer or equivalent?
Or a varicap parametric amplifier? They were a fad for a while, before
fet opamps got good. I think TI even made a monolithic varactor-based
opamp once.
John