Problem in TX_MAC_CTRL visible when sending packets with long pauses between

[wzab]

Hi,

I have faced a problem in opencores-tri-mode eth MAC, when I had to
send bursts of packets with quite long puses between them.
The whole problem and found workaround is decribed in the bugtracker:
http://opencores.org/bug,view,2061
However the bugtracker corrupted the patch file, therefore I send it
here.
I'd appreciate more elegant solution of the problem (which is too late
update of Fifo_ra signal, causing erroneous entering of StatePreamble
after the last packet is sent), which is now cured by adding of an
additional StateIdle2 state in Tx_MAC_Ctrl.
--
HTH & Regards,
Wojtek

Patch follows:

*** /tmp/MAC_tx_Ctrl.v 2006-06-25 06:59:00.000000000 +0200
--- MAC_tx_Ctrl.v 2011-10-09 11:43:32.544538167 +0200
***************
*** 174,179 ****
--- 174,180 ----
parameter StateSwitchNext =4'd12;
parameter StateDefer =4'd13;
parameter StateSendPauseFrame =4'd14;
+ parameter StateIdle2 =4'd15;

reg [3:0] Current_state /*synthesis syn_keep=1 */;
reg [3:0] Next_state;
***************
*** 277,282 ****
--- 278,285 ----
else
Next_state=Current_state;
StateIdle:
+ Next_state=StateIdle2;
+ StateIdle2:
if (!FullDuplex&&CRS)
Next_state=StateDefer;
else if (pause_apply)

[wzab]

Today I have found, that it is necessary to add yet another "wait
state" - StateIdle3.

Below is the patch which I have used to modify the original
MAC_tx_Ctrl.v
After this change, the design seems to work reliably

*** /tmp/MAC_tx_Ctrl.v 2006-06-25 06:59:00.000000000 +0200

--- MAC_tx_Ctrl.v 2011-10-10 20:56:27.121148241 +0200
***************
*** 159,182 ****
//
******************************************************************************
//internal
signals
//
******************************************************************************
! parameter StateIdle =4'd00;
! parameter StatePreamble =4'd01;
! parameter StateSFD =4'd02;
! parameter StateData =4'd03;
! parameter StatePause =4'd04;
! parameter StatePAD =4'd05;
! parameter StateFCS =4'd06;
! parameter StateIFG =4'd07;
! parameter StateJam =4'd08;
! parameter StateBackOff =4'd09;
! parameter StateJamDrop =4'd10;
! parameter StateFFEmptyDrop =4'd11;
! parameter StateSwitchNext =4'd12;
! parameter StateDefer =4'd13;
! parameter StateSendPauseFrame =4'd14;

! reg [3:0] Current_state /*synthesis syn_keep=1 */;
! reg [3:0] Next_state;
reg [5:0] IFG_counter;
reg [4:0] Preamble_counter;//
reg [7:0] TxD_tmp ;
--- 159,184 ----
//
******************************************************************************
//internal
signals
//
******************************************************************************
! parameter StateIdle =5'd00;
! parameter StatePreamble =5'd01;
! parameter StateSFD =5'd02;
! parameter StateData =5'd03;
! parameter StatePause =5'd04;
! parameter StatePAD =5'd05;
! parameter StateFCS =5'd06;
! parameter StateIFG =5'd07;
! parameter StateJam =5'd08;
! parameter StateBackOff =5'd09;
! parameter StateJamDrop =5'd10;
! parameter StateFFEmptyDrop =5'd11;
! parameter StateSwitchNext =5'd12;
! parameter StateDefer =5'd13;
! parameter StateSendPauseFrame =5'd14;
! parameter StateIdle2 =5'd15;
! parameter StateIdle3 =5'd16;

! reg [4:0] Current_state /*synthesis syn_keep=1 */;
! reg [4:0] Next_state;
reg [5:0] IFG_counter;
reg [4:0] Preamble_counter;//
reg [7:0] TxD_tmp ;
***************
*** 277,282 ****
--- 279,288 ----

else
Next_state=Current_state;
StateIdle:
+ Next_state=StateIdle2;
+ StateIdle2:

+ Next_state=StateIdle3;
+ StateIdle3: