error_code asm

[Michael Brennan]

Hi!
A litte thing I noticed and wonder about. I looked at error_code in
arch/i386/kernel/entry.S. And this is how it starts (in 2.6.7):

error_code:
pushl %ds
pushl %eax
xorl %eax, %eax
pushl %ebp
pushl %edi
pushl %esi
pushl %edx
decl %eax # eax = -1
pushl %ecx
pushl %ebx

My question is why the 'decl %eax' is 4 lines after the clearing of eax 'xorl
%eax %eax'. Can't it just be put right after xorl?

Of course you can put it anywhere you want, but I wonder if there is a
particular reason to put it there, or is just some personal taste?

/Michael

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[Timur Tabi]

Michael Brennan wrote:

> error_code:
> pushl %ds
> pushl %eax
> xorl %eax, %eax
> pushl %ebp
> pushl %edi
> pushl %esi
> pushl %edx
> decl %eax # eax = -1
> pushl %ecx
> pushl %ebx
>
> My question is why the 'decl %eax' is 4 lines after the clearing of eax 'xorl
> %eax %eax'. Can't it just be put right after xorl?

It's for CPU pipeline optimization.

--
Timur Tabi
Staff Software Engineer
timur...@ammasso.com

[Michael Brennan]

On Tuesday 28 September 2004 22.49, Timur Tabi wrote:
> Michael Brennan wrote:
> > error_code:
> > pushl %ds
> > pushl %eax
> > xorl %eax, %eax
> > pushl %ebp
> > pushl %edi
> > pushl %esi
> > pushl %edx
> > decl %eax # eax = -1
> > pushl %ecx
> > pushl %ebx
> >
> > My question is why the 'decl %eax' is 4 lines after the clearing of eax
> > 'xorl %eax %eax'. Can't it just be put right after xorl?
>
> It's for CPU pipeline optimization.

ok. i see.

Can anyone tell me where I can read more about optimizing for pipelining? I
searched the internet and looked in the intel specifications, but I only find
explanations on how the pipelining and prefetching works, not how to optimize
for it.

Could someone at least tell me how the optimization works in this example? (if
its not far too complex, then I'll forget about it)

/Michael

[Brandon Niemczyk]

On Wed, 29 Sep 2004 01:54:58 +0200, Michael Brennan <mbre...@ezrs.com> wrote:
> On Tuesday 28 September 2004 22.49, Timur Tabi wrote:
> > Michael Brennan wrote:
> > > error_code:
> > > pushl %ds
> > > pushl %eax
> > > xorl %eax, %eax
> > > pushl %ebp
> > > pushl %edi
> > > pushl %esi
> > > pushl %edx
> > > decl %eax # eax = -1
> > > pushl %ecx
> > > pushl %ebx
> > >
> > > My question is why the 'decl %eax' is 4 lines after the clearing of eax
> > > 'xorl %eax %eax'. Can't it just be put right after xorl?
> >
> > It's for CPU pipeline optimization.
>
> ok. i see.
>
> Can anyone tell me where I can read more about optimizing for pipelining? I
> searched the internet and looked in the intel specifications, but I only find
> explanations on how the pipelining and prefetching works, not how to optimize
> for it.

http://webster.cs.ucr.edu/AoA/Linux/HTML/CPUArchitecturea3.html#1014785

just knowing how pipelining and prefetching works will bring you a long way.

>
> Could someone at least tell me how the optimization works in this example? (if
> its not far too complex, then I'll forget about it)

there's time for the xor to finish before %eax is accessed again, so
that there isn't a pipeline stall.

>
> /Michael
>
>
>
>
> --
> Kernelnewbies: Help each other learn about the Linux kernel.
> Archive: http://mail.nl.linux.org/kernelnewbies/
> FAQ: http://kernelnewbies.org/faq/
>
>

--
Brandon Niemczyk
http://bniemczyk.doesntexist.com