#### ED & TC 96 Call for Papers ####
Bernard Courtois
<URL:http://www.iao.fhg.de/Library/conferences>.
---------------------------------------------------------------------------
************************************************
* The European Design and Test Conference 1996 *
* - From ASICs to Systems - *
* Paris, France, March 11-14, 1996 *
************************************************
EDAC ETC ASIC
Sponsored by EDAA, by the IEEE Computer Society,
and by ACM SIG-DA
CALL FOR PAPERS
Scope of the Conference
-----------------------
In the context of electronic and electromechanical products ranging from
integrated circuits through multi-chip modules and printed-circuit boards
to full systems, the conference it deals with:
1- The actual design of such products. Emphasis is on challenges and
experiences concerning the design of advanced electronic components
and systems.
2- The entire field of Design Automation and tools for such products.
Emphasis is on methods and tools employed in all aspects of the use of
computers for designing products. This includes fully automatic as well
as computer-guided approaches, data management techniques and user
interfaces.
3- Testing of electronic products. This includes testing of digital, mixed
digital/analogue and analogue circuits and systems, test program
development, test systems and design for testability.
ED&TC covers the scope of the originally separate conferences EDAC
and ETC. The 1996 European Design and Test Conference is sponsored
by the EDA Association, a non-profit association of European DA
professionals, by the IEEE Computer Society, and by ACM SIG-DA. It
is held in cooperation with the IEEE Circuits and Systems Society and
other European Societies.
Aims
----
The aim is to meet the much needed requirement for an international
conference with a European flavour to provide a significant focus and
forum for Electrical Engineering professionals. The intention is to
establish a forum for the presentation of outstanding industrial and
academic technical work in the above mentioned areas. The need for such
a forum comes from the increasing specialisation of application areas,
which requires a closer link between Design, Testing and Design
Automation. The 1996 event will give the opportunity to designers and
test engineers to exchange information and requirements on CAD, CAT
and ATE, and to obtain information on the latest developments in all
these areas. Panels, tutorials, fringe meetings, awards, and a University
Booth will be part of the conference. In 1995, the joint conference had
400 paper submissions from which international reviewers selected high-
quality papers for presentation at the conference. This number of
submission has made the joint conference the largest European event in
its area.
Exhibition
----------
An Exhibition will be held from March 12 to March 14, 1996, in parallel
with the conference, and will be open free of charge to all attendees. It is
expected that over 100 exhibitors specialising in CAD, ASIC design,
ATE and CAT tools will participate. Those requiring exhibition space
should contact the Exhibition Secretariat.
Location
--------
The Conference & Exhibition will be held in the prestigious CNIT
Conference and Exhibition Centre, located in Paris-La Defense, near to
La Grande Arche, and only a 10 minute "metro" ride from downtown
Paris.
Information
-----------
Conference Secretariat: Exhibition Secretariat:
CEP Consultants Ltd EDA Exhibitions Ltd.
43 Manor Place 31-33 High Holborn
Edinburgh, EH3 7EB, UK London WC1V 6BD, UK
Phone: +44 131 300 3300 Phone: +44-171-404 0564
Fax: +44 131 300 3400 Fax: +44-171-831 2057
General Chair: C. Lopez Barrio
Vice-General Chair: L. Eggermont
Programme Chair: P. Marwedel
User's Forum Chair: G. Saucier
Deadlines and Key Dates
Submission of Manuscripts September 8, 1995
Notification of Acceptance November 10, 1995
Final version of manuscript due December 15, 1995
Pre-Conference Tutorials March 11, 1996
Conference Sessions March 12-14, 1996
Exhibition March 12-14, 1996
Areas of Interest
-----------------
Original technical papers on (but not limited to) the following topis are
invited:
1- Full System Design:
Actual industrial or academic designs, applications of E-CAD; consumer
electronics, telecommunications, automotive electronics, computers,
electromechanical systems; power-management.
2- Digital ASIC and ASIP Design:
Actual industrial or academic designs; design of advanced chips and chip-
sets; experimentation with advanced CAD tools and methodologies; use
of tools and libraries, component modelling; power-management;
package design.
3- Design and Test of Analogue and Mixed Analogue/Digital Systems:
Actual industrial or academic designs; simulation techniques and
analytical models for mixed systems;
Synthesis and DfT techniques for mixed systems; mixed-signal test.
4- System Design Technologies:
Specification languages and paradigms; system design techniques and
tools; framework technologies; partitioning; software-hardware codesign;
code generation for embedded processors; concurrent engineering,
design modelling.
5- Architectural Synthesis:
Synthesis at the architectural level; high-level synthesis; architectural
trade-offs; performance and cost driven architectural synthesis; timing
and power issues; VHDL for synthesis.
6- Logic and finite state machine synthesis:
Combinational logic synthesis; technology mapping; hierarchical
controller synthesis; state assignment; synthesis of testable controllers;
performance driven synthesis and power control; PLD and FPGA
synthesis; timing issues.
7- Digital Simulation and Emulation:
Advanced simulation techniques from systems to circuit level; simulation
languages (including VHDL and Verilog); simulation accelerators;
emulation techniques; embedded hardware-software simulation; analytical
models; emulation of large systems.
8- Formal Verification:
Formal techniques and methods for verification; design correctness; use
of automatic theorem provers; symbolic manipulation; formal
specification languages; transformational design; theory of BDDs.
9- Layout Synthesis and Verification for VLSI, Boards and MCMs:
Automatic place and route; performance and power driven layout;
analogue and digital cell layout rule checking and characterisation;
electrical verification; modelling and characterisation of on and off chip
interconnects.
10- Design and Synthesis for Testability of Digital Systems
Internal scan; macro test; boundary-scan; built-in self test; IDDQ
testability; Proven < 50 PPM DfT schemes; testability planning for
systems, ASICs, embedded processors, and communication protocols;
partitioning for testability; system reliability issues.
11- Test Program Development Tools and Techniques:
Pattern generation; test pattern generation for memories; fault simulation;
expert systems; inductive fault analysis; languages and standards.
12- Component, MCM, Board and System Testing:
ATE hardware and software; test-pattern application; fixturing; pin
electronics; diagnostic techniques; VXI bus systems; IDDQ-test-
hardware; functional and structural approaches and safety-critical
applications; 1149.1, 1149.2, 1149.4, micro-computer based self-test.
13- Methods and Tools for the Design of Microsystems:
CAD tools for the design and test of micromechanical systems,
microengines and sensors.
Submit manuscripts to:
---------------------
Conference Secretariat: For information:
CEP Consultants Ltd. phone: +44 131 300 3300
43 Manor Place fax: +44 131 300 3400
Edinburgh, EH3 7EB, UK
Submission of Papers
--------------------
Two different categories of papers are distinguished:
1) Submissions for the formal proceedings:
Papers on design, CAD and test from a scientific perspective. Full-
length, unpublished papers which will be reviewed for their scientific
contents and, if accepted, included in the proceedingspublished by IEEE.
Contributions in this category are expected to advance the current state-
of-the art in design, CAD or test technologies.
Each submission should include nine stapled copies of the complete
manuscript. Each copy should include:
- The Title Page
This page should state the title, the names, affiliations and addresses of
all authors, together with the identification, telephone number, fax
number, and e-mail address of the principal author, and a list of ED&TC
topic numbers (see above), ordered by relevancy.
On your submission, please mention clearly, whether your paper is
intended to be published in the formal proceedings or in the User's
Forum volume. The cover page should also include the following signed
statement:
All appropriate clearances for the publication of this paper have been
obtained, and if accepted the author will prepare the final manuscript in
time for inclusion in the Conference Proceedings and will present the
paper at the Conference.
- An Abstract Page.
This page should contain an abstract of about 60 words.
-The complete draft of the paper.
The draft should include an outline of all illustrations and references and
should not exceed 12 pages (double spaced A4 or equivalent, font > or = 12).
The international review panel will give high preference to papers that,
excluding references, figures and tables, do not exceed 3000 words to
clearly present the work, methods, results, originality, significance,
superiority and applications of the techniques discussed.
Excessively long contributions will be returned to the authors. As far as
possible, although there will be an opportunity to update the paper from
an extended abstract, the submitted manuscript should closely reflect the
final paper as it will appear in the Proceedings, which will be 5 pages,
double column format.
Any submissions which are received by fax will not be processed.
2) Submissions for the User's Forum:
Papers on design, CAD and test from a user's or vendor's perspective.
In this category, submission of extended summaries of up to 1500 words
is sufficient. Submissions will be reviewed and, if accepted, published in
a separate User's Forum volume. Papers on the following areas are
especially welcome for
this category: practical applications, case studies, tradeoff analyses,
competitiveness of target technologies, risk evaluations, industrial
products, economical ASIC feasibility studies, surveys, state-of-the-art
presentations.
ASIC Prize:
-----------
Any paper submitted, for either of the two categories, describing the
design of a manufactured ASIC is a candidate for the "ASIC Prize".
ASIC Prizes will be attributed to papers describing the most original and
practical experiences in ASIC design.
--
************************************************************************
Bernard Courtois -TIMA-CMP- Bernard....@imag.fr | Tel: (+33)76574615
46 avenue Felix Viallet, 38031 Grenoble Cedex, France | Fax: (+33)76473814
http://tima-cmp.imag.fr/Homepages/courtois/courtois.html