[Iwls] Call for Papers: ASYNC'2010 Symposium
Steven Nowick
[Our apologies if you receive multiple copies of this CFP]
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ASYNC 2010
The 16th IEEE International Symposium on Asynchronous Circuits and Systems
3rd - 6th May 2010
Grenoble, France
To be held in conjunction with
The 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010)
http://www.minatec.org/async-nocs2010/
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CALL FOR PAPERS
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Technical Scope
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The International Symposium on Asynchronous Circuits and Systems is the premier
forum for researchers to present their latest findings in the area of
asynchronous design. Authors are invited to submit full papers on any aspect of
asynchronous design, ranging from the core topics of design, synthesis and
test, to asynchronous applications in system-level integration and emerging
computing technologies. Topics of interest include, but are not limited to:
* Asynchronous/mixed-timed circuits, architectures, memories and interfaces,
including interfaces with analogue and mixed-signal domains.
* Design models and methods for asynchronous buses, Networks-on-Chip (NoC),
System-on-Chip (SoC) and multi-chip interconnects.
* Asynchronous power-adaptive computing, ultra-low power systems, electronics
for energy harvesting.
* Asynchrony in emerging technologies, including genetic, neural, nano and
quantum computing.
* Embedded system design with asynchronous architectures/implementations.
* Elastic and latency-tolerant synchronous design and GALS systems.
* Synchronization, arbitration, metastability modeling and analysis.
* CAD tools for asynchronous design, synthesis, analysis and optimization.
* Physical design of asynchronous logic and pipelines.
* Formal methods for correctness, and performance/power analysis.
* Test, reliability, security, and radiation tolerance.
* Asynchronous variability-tolerant design and design for manufacturing.
* Motivating case studies, comparisons, and applications.
Papers will be evaluated by the program committee in a blind review process on
the basis of scientific merit, innovation, relevance, and presentation.
New idea papers are encouraged, and the program committee recognizes that
such papers may contain different evaluation criteria based on the lower
maturity of novel technology than papers in established areas. Accepted papers
will be published in IEEE conference proceedings.
Several selected papers with highest review scores from the ASYNC 2010 program
will be invited for submission to a Special Issue of IET Computers and
Digital Techniques on the Recent Advances in Asynchronous System Design, which
is planned to appear early in 2011.
This year, ASYNC 2010 will be collocated with the 4th ACM/IEEE International
Symposium on Networks-on-Chip (NOCS 2010). The organization and the programs of
both symposia will be jointly coordinated, including keynote lectures,
tutorials, exhibitions and social events.
For further information, see the ASYNC web site:
http://asyncsymposium.org/async2010/
Conference Committee
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General Chairs Pascal Vivet, CEA-Leti, France
Marc Renaudin, Tiempo, France
Program Chairs Alex Yakovlev, Newcastle Univ., UK
Ken Stevens, Univ. of Utah, USA
Invited Speakers Chair Ran Ginosar, Technion, Israel
Publication Chair Erik Brunvand, Univ. of Utah, USA
Publicity Chair Steven Nowick, Columbia University, USA
Tutorials Chair Laurent Fesquet, TIMA lab., France
Best Paper Chair Jordi Cortadella, UPC, Spain
Industrial Liaison Chairs Marly Roncken, Portland State U., USA
John Bainbridge, Silistix, UK
Web Chair Montek Singh, UNC Chapell Hill, USA
Finance Chair Yvain Thonnart, CEA-Leti, France
Local Arrangement Pascal Vivet, CEA-Leti, France
Important Dates
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Abstract registration: November 30, 2009
Full paper submission: December 7, 2009
Notification of acceptance: February 1st, 2010
Final version due: March 1st, 2010
Paper Format
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Abstract of up to 150 words, 10 pages or fewer, including figures and
bibliography, single spaced, 10pt or larger font size, IEEE double
column conference format.
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