Reviewers: Karl,
Description:
Remove tst+ldr, tst+str from checked-in nexes.
This is in preparation for my CL which conditionally supports this
sandboxing sequence. This change would otherwise fail the trybots
because they can't diff nexes properly.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3117
R=kschi...@google.com
Please review this at https://codereview.chromium.org/11348120/
SVN Base: svn://svn.chromium.org/native_client/trunk/src/native_client
Affected files:
M src/trusted/validator_arm/testdata/test_loads.S
M src/trusted/validator_arm/testdata/test_loads.err
M src/trusted/validator_arm/testdata/test_loads.nexe
M src/trusted/validator_arm/testdata/test_stores.S
M src/trusted/validator_arm/testdata/test_stores.err
M src/trusted/validator_arm/testdata/test_stores.nexe
Index: src/trusted/validator_arm/testdata/test_loads.S
diff --git a/src/trusted/validator_arm/testdata/test_loads.S
b/src/trusted/validator_arm/testdata/test_loads.S
index
a6d34de7e8b1fcb4faa87163b780a269c869821d..24f3140a7f61c4c92a7a4f03124dd273b 045a677
100644
--- a/src/trusted/validator_arm/testdata/test_loads.S
+++ b/src/trusted/validator_arm/testdata/test_loads.S
@@ -79,17 +79,3 @@ bundle9:
ldr r1, [sp], r2 @ post-indexing sp by a register is an ERROR
nop
nop
-
-
-conditional_sandbox:
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- ldreq r1, [r0] @ load: should work.
-
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- ldr r1, [r0] @ load unconditionally: ERROR.
-
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- ldrgt r1, [r0] @ load using wrong predicate: ERROR.
-
- tsteq r0, #0xC0000000 @ Conditionally set Z if the top two bits are
clear,
- ldrgt r1, [r0] @ and load using wrong predicate: ERROR.
Index: src/trusted/validator_arm/testdata/test_loads.err
diff --git a/src/trusted/validator_arm/testdata/test_loads.err
b/src/trusted/validator_arm/testdata/test_loads.err
index
6ec6867cadac9096f248538edf0346db3bd491b0..bf8998c61803003e724e4ae997e34b36b ed06f84
100644
--- a/src/trusted/validator_arm/testdata/test_loads.err
+++ b/src/trusted/validator_arm/testdata/test_loads.err
@@ -1,13 +1,10 @@
-ncval: 00020014 Load/store base r1 is not properly masked.
-ncval: 0002001c Load/store base r1 is not properly masked.
-ncval: 00020030 Load/store base register is not properly masked, because
instruction pair [0002002c, 00020030] crosses bundle boundary.
-ncval: 00020044 Load/store base r2 is not properly masked.
-ncval: 0002005c Load/store base r0 is not properly masked.
-ncval: 00020064 Instruction has operand(s) forbidden by Native Client.
-ncval: 00020064 Destination branch on pc is not properly masked.
-ncval: 0002006c Updating sp without masking in following instruction.
-ncval: 00020084 Instruction not allowed by Native Client.
-ncval: 00020094 Updating sp without masking in following instruction.
-ncval: 000200ac Load/store base r0 is not properly masked, because
000200ac is not conditional on EQ.
-ncval: 000200b4 Load/store base r0 is not properly masked, because
000200b4 is not conditional on EQ.
-ncval: 000200bc Load/store base r0 is not properly masked, because
000200bc is not conditional on EQ.
+ncval: 00038684 Load/store base r1 is not properly masked.
+ncval: 0003868c Load/store base r1 is not properly masked.
+ncval: 000386a0 Load/store base register is not properly masked, because
instruction pair [0003869c, 000386a0] crosses bundle boundary.
+ncval: 000386b4 Load/store base r2 is not properly masked.
+ncval: 000386cc Load/store base r0 is not properly masked.
+ncval: 000386d4 Instruction has operand(s) forbidden by Native Client.
+ncval: 000386d4 Destination branch on pc is not properly masked.
+ncval: 000386dc Updating sp without masking in following instruction.
+ncval: 000386f4 Instruction not allowed by Native Client.
+ncval: 00038704 Updating sp without masking in following instruction.
Index: src/trusted/validator_arm/testdata/test_loads.nexe
diff --git a/src/trusted/validator_arm/testdata/test_loads.nexe
b/src/trusted/validator_arm/testdata/test_loads.nexe
index
0b59b8cf9623ae91699d0ca53f8f3ae06fd77560..c083fc6820061de932d0e6f09ff8e0297 9bc4b24
100755
Binary files a/src/trusted/validator_arm/testdata/test_loads.nexe and
b/src/trusted/validator_arm/testdata/test_loads.nexe differ
Index: src/trusted/validator_arm/testdata/test_stores.S
diff --git a/src/trusted/validator_arm/testdata/test_stores.S
b/src/trusted/validator_arm/testdata/test_stores.S
index
2be3ce4c492368f20494abe2ce96b0b639b3b389..40473d45c39e00b654003993277cc94d7 57345d7
100644
--- a/src/trusted/validator_arm/testdata/test_stores.S
+++ b/src/trusted/validator_arm/testdata/test_stores.S
@@ -59,16 +59,3 @@ bundle6:
str r1, [sp], r2 @ post-indexing sp by a register is an ERROR
bic r0, r0, #0xC0000000 @ Mask a register, and
str r1, [r0, r2] @ use it in register pre-index store: ERROR
-
-conditional_sandbox:
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- streq r1, [r0] @ store: should work.
-
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- str r1, [r0] @ store unconditionally: ERROR.
-
- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and
- strgt r1, [r0] @ store using wrong predicate: ERROR.
-
- tsteq r0, #0xC0000000 @ Conditionally set Z if the top two bits are
clear,
- strgt r1, [r0] @ and store using wrong predicate: ERROR.
Index: src/trusted/validator_arm/testdata/test_stores.err
diff --git a/src/trusted/validator_arm/testdata/test_stores.err
b/src/trusted/validator_arm/testdata/test_stores.err
index
1b213e9bcd1c13e865004714f09fc3a04a0c6f2d..88b1452c17cd0e0ce6ce4055dcba97517 16a0663
100644
--- a/src/trusted/validator_arm/testdata/test_stores.err
+++ b/src/trusted/validator_arm/testdata/test_stores.err
@@ -1,10 +1,7 @@
-ncval: 00020014 Load/store base r1 is not properly masked.
-ncval: 0002001c Load/store base r1 is not properly masked.
-ncval: 00020030 Load/store base register is not properly masked, because
instruction pair [0002002c, 00020030] crosses bundle boundary.
-ncval: 00020044 Load/store base r2 is not properly masked.
-ncval: 0002005c Load/store base r0 is not properly masked.
-ncval: 00020064 Updating sp without masking in following instruction.
-ncval: 0002006c Instruction not allowed by Native Client.
-ncval: 0002007c Load/store base r0 is not properly masked, because
0002007c is not conditional on EQ.
-ncval: 00020084 Load/store base r0 is not properly masked, because
00020084 is not conditional on EQ.
-ncval: 0002008c Load/store base r0 is not properly masked, because
0002008c is not conditional on EQ.
+ncval: 00038684 Load/store base r1 is not properly masked.
+ncval: 0003868c Load/store base r1 is not properly masked.
+ncval: 000386a0 Load/store base register is not properly masked, because
instruction pair [0003869c, 000386a0] crosses bundle boundary.
+ncval: 000386b4 Load/store base r2 is not properly masked.
+ncval: 000386cc Load/store base r0 is not properly masked.
+ncval: 000386d4 Updating sp without masking in following instruction.
+ncval: 000386dc Instruction not allowed by Native Client.
Index: src/trusted/validator_arm/testdata/test_stores.nexe
diff --git a/src/trusted/validator_arm/testdata/test_stores.nexe
b/src/trusted/validator_arm/testdata/test_stores.nexe
index
f3851f73efa3b00c9842b0e0c0666ea1ce61c48c..1520888920d8e73200957ec992f3cffb6 13048da
100755
Binary files a/src/trusted/validator_arm/testdata/test_stores.nexe and
b/src/trusted/validator_arm/testdata/test_stores.nexe differ
