You need a cell library that has real delays in the models of the gates. You can download one from my course website at http://www.uccs.edu/~gtumbush/4242/OSU_cell_library/osu_cell_library.html Just click on “Verilog model for cell library”. You need to compile the cell library just like a module.
Greg Tumbush, Ph.D., P.E.
Instructor
University of Colorado, Colorado Springs
ENGR 222
1420 Austin Bluffs Parkway
Colorado Springs, Colorado 80933-7150
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§ gate delays [1 Update]
sjmp65 <sjma...@gmail.com> Oct 26 03:51PM -0700
I am a student and we are studying gate delays and timing diagrams. We
have difficult diagrams and wanted to simulate the gates to see what
the wave forms would look like. I looked on the internet and I can’t
find anything that instructs on implementing delays. Is this possible?
I am trying to simulate an SR flip flop
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