router architecture help

[yasemin poyraz]

Hello,
I 'm working about router architecture. ı hove to design a router.
router does not have to be very complex. it has only two
interface(input and output). But it's difficult for me.router get a
packet . Packet comes with IPv6 addressing header. Header information
decide outgoing port. it has routing table, to store packet memory and
cpu computing general process. I know what include for this router
but ı have to decide input and output port lenght. memory lenght. this
step is difficult for me. Is there anyone who can help in this regard?
I implement this router on simulation environment with verilog
language.

[최익성]

Dear Yasemin Poyraz.

I hope the followings are helpful to you.

Input/output port length?

The router determines the outgoing link(port) by using IPv6 address/Ethernet address in packet/frame header.

This step is called lookup from address to output link.

Packet can be classified into several types. Usually control packets are delivered to processor(CPU). 

and the processor performs control jobs such as routing table update, traffic/flow specification update, filtering, discarding, actions for traffic groups, etc.

I expect the lookup can be simplified by using novel techniques such source routing, ... ?.

I don't know what the "input/output port length" means in your question

The bandwidth of router is determined by "link bandwidth * #links(ports)".

In routing system, the memory constraints and specification are determined by the input/output link bandwidth and cell/packet length.

Usually, the packet is segmented into multiple fixed length cells in router. 

Commercial products use their own cell length among 40 ~ 80 bytes (for eaxample, 64, 72, 80 bytes). You can find an example of ATM system.

In the other systems, the packet can be processed without segmentation, or mulitiple packets can be merged into a very long packet (mega packet).

In worm-hole routing system, the packet receiving/sending/routing(switching) can be processed simultaneously.

If I take a example of memory size/length.

In case of 1 Gbit/s link, if you can use 10 bit datapath(memory width) operating at 100Mhz clock, 40 bytes cell can be stored in 32 (4*8) clocks.

In this case, the memory width = 10 bit, the memory depth for a cell is 32. You can use a RAM to store multiple cells.

In real systems, there are some bandwidth overheads (internal header, ...).

I wish your success.

2012년 1월 9일 월요일 오후 6시 43분 57초 UTC+9, yasemin poyraz 님의 말: