system verilog ovm support

[pallavik7]

Hi

I am working on a project where I am trying to develop an OVM based
test environment is systemverilog for a verilog core..I would like to
know if the student PE edition would support this ? Anyone who has
used this feature, please do let me know.

Thanks
Pallavi Khandelwal.

[Prem]

Hi Pallavi,

I also have the same requirement, please share if U know some solution.

Best regards,
Prem.

[Aman Kharbanda]

No, UVM methodology won't be supported in PE edition