URL: http://llvm.org/viewvc/llvm-project?rev=131455&view=rev
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Modified:
    llvm/trunk/lib/Target/X86/README.txt

Modified: llvm/trunk/lib/Target/X86/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README....
=========================================================================== ===
--- llvm/trunk/lib/Target/X86/README.txt (original)
+++ llvm/trunk/lib/Target/X86/README.txt Tue May 17 02:22:33 2011
@@ -2040,3 +2040,29 @@
 The move of 0 could be scheduled above the test to make it is xor reg,reg.

 //===---------------------------------------------------------------------= ==//
+
+GCC PR48986.  We currently compile this:
+
+void bar(void);
+void yyy(int* p) {
+    if (__sync_fetch_and_add(p, -1) == 1)
+      bar();
+}
+
+into:
+       movl    $-1, %eax
+       lock
+       xaddl   %eax, (%rdi)
+       cmpl    $1, %eax
+       je      LBB0_2
+
+Instead we could generate:
+
+       lock
+       dec %rdi
+       je LBB0_2
+
+The trick is to match "fetch_and_add(X, -C) == C".
+
+//===--------------------------------------------------------------------- ===//
+

you probably meant dec (%rdi) ?