[PATCHv3] dmaengine: Add support for BCM2835

[Florian Meier]

Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
Currently it only supports cyclic DMA.

Signed-off-by: Florian Meier <floria...@koalo.de>
---

Thank you for your comments!
I hope I have now removed all leftovers of the sg struct.
Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I chose uint32_t. If you think fixed le32 is more likely I will change it.
The PAD fields do not seem to be used, but the datasheet states they should be set to 0.


.../devicetree/bindings/dma/bcm2835-dma.txt | 57 ++
arch/arm/boot/dts/bcm2835.dtsi | 23 +
drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +
drivers/dma/bcm2835-dma.c | 810 ++++++++++++++++++++
5 files changed, 897 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/bcm2835-dma.txt
create mode 100644 drivers/dma/bcm2835-dma.c

diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
new file mode 100644
index 0000000..9542ac8
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
@@ -0,0 +1,57 @@
+* BCM2835 DMA controller
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-dma".
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain all DMA interrupts. First cell is the IRQ bank
+ Second cell is the IRQ number.
+- #dma-cells: Must be <1>, used to represent the number of integer cells in
+the dmas property of client devices.
+- dma-channels: Maximum number of DMA channels available
+- dma-requests: Number of DMA Requests.
+- dma-channel-mask: Bit mask representing the channels available.
+
+Example:
+
+dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16
+ 1 17
+ 1 18
+ 1 19
+ 1 20
+ 1 21
+ 1 22
+ 1 23
+ 1 24
+ 1 25
+ 1 26
+ 1 27
+ 1 28>;
+
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ dma-requests = <32>;
+ dma-channel-mask = <0x7f35>;
+};
+
+DMA clients connected to the BCM2835 DMA controller must use the format
+described in the dma.txt file, using a two-cell specifier for each channel:
+a phandle plus one integer cells.
+The two cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. The DREQ number.
+
+Example:
+
+bcm2835_i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+ reg = < 0x7e203000 0x20
+ 0x7e101098 0x02>;
+
+ dmas = <&dma 2
+ &dma 3>;
+ dma-names = "tx", "rx";
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 1e12aef..7389405 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -103,6 +103,29 @@
clocks = <&clk_mmc>;
status = "disabled";
};
+
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16
+ 1 17
+ 1 18
+ 1 19
+ 1 20
+ 1 21
+ 1 22
+ 1 23
+ 1 24
+ 1 25
+ 1 26
+ 1 27
+ 1 28>;
+
+ #dma-cells = <1>;
+ dma-channels = <15>; /* DMA channel 15 is not handled yet */
+ dma-requests = <32>;
+ dma-channel-mask = <0x7f35>;
+ };
};

clocks {
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f238cfd..f2d253b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -288,6 +288,12 @@ config DMA_OMAP
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS

+config DMA_BCM2835
+ tristate "BCM2835 DMA engine support"
+ depends on (ARCH_BCM2835 || MACH_BCM2708)
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+
config TI_CPPI41
tristate "AM33xx CPPI41 DMA support"
depends on ARCH_OMAP
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index db89035..6348157 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
+obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
new file mode 100644
index 0000000..141a698
--- /dev/null
+++ b/drivers/dma/bcm2835-dma.c
@@ -0,0 +1,810 @@
+/*
+ * BCM2835 DMA engine support
+ *
+ * This driver only supports cyclic DMA transfers
+ * as needed for the I2S module.
+ *
+ * Author: Florian Meier, <floria...@koalo.de>
+ * Copyright 2013
+ *
+ * based on
+ * OMAP DMAengine support by Russell King
+ *
+ * BCM2708 DMA Driver
+ * Copyright (C) 2010 Broadcom
+ *
+ * Raspberry Pi PCM I2S ALSA Driver
+ * Copyright (c) by Phil Poole 2013
+ *
+ * MARVELL MMP Peripheral DMA Driver
+ * Copyright 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+
+#include "virt-dma.h"
+
+struct bcm2835_dmadev {
+ struct dma_device ddev;
+ spinlock_t lock;
+
+ uint32_t chans_available;
+
+ void __iomem *dma_base;
+ int *dma_irq_numbers;
+
+ struct device_dma_parameters dma_parms;
+};
+
+struct bcm2835_dma_cb {
+ uint32_t info;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t length;
+ uint32_t stride;
+ uint32_t next;
+ uint32_t pad[2];
+};
+
+struct bcm2835_chan {
+ struct virt_dma_chan vc;
+ struct list_head node;
+
+ struct dma_slave_config cfg;
+ unsigned dma_sig;
+ bool cyclic;
+ unsigned dreq;
+
+ int dma_ch;
+ struct bcm2835_desc *desc;
+
+ void __iomem *dma_chan_base;
+ int dma_irq_number;
+};
+
+struct bcm2835_desc {
+ struct virt_dma_desc vd;
+ enum dma_transfer_direction dir;
+ dma_addr_t dev_addr;
+
+ unsigned int control_block_size;
+ struct bcm2835_dma_cb *control_block_base;
+ dma_addr_t control_block_base_phys;
+
+ unsigned frames;
+};
+
+#define BCM2835_DMA_CS 0x00
+#define BCM2835_DMA_ADDR 0x04
+#define BCM2835_DMA_SOURCE_AD 0x0c
+#define BCM2835_DMA_DEST_AD 0x10
+#define BCM2835_DMA_NEXTCB 0x1C
+
+/* DMA CS Control and Status bits */
+#define BCM2835_DMA_ACTIVE (1 << 0)
+#define BCM2835_DMA_INT (1 << 2)
+#define BCM2835_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
+#define BCM2835_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
+#define BCM2835_DMA_ERR (1 << 8)
+#define BCM2835_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
+#define BCM2835_DMA_RESET (1 << 31) /* WO, self clearing */
+
+#define BCM2835_DMA_INT_EN (1 << 0)
+#define BCM2835_DMA_D_INC (1 << 4)
+#define BCM2835_DMA_D_DREQ (1 << 6)
+#define BCM2835_DMA_S_INC (1 << 8)
+#define BCM2835_DMA_S_DREQ (1 << 6)
+
+#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
+
+#define BCM2835_DMA_DATA_TYPE_S8 1
+#define BCM2835_DMA_DATA_TYPE_S16 2
+#define BCM2835_DMA_DATA_TYPE_S32 4
+#define BCM2835_DMA_DATA_TYPE_S128 16
+
+/* valid only for channels 0 - 14, 15 has its own base address */
+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* base address */
+#define BCM2835_DMA_CHANIO(dma_base, n) ((dma_base) + BCM2835_DMA_CHAN(n))
+
+static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
+{
+ return container_of(d, struct bcm2835_dmadev, ddev);
+}
+
+static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct bcm2835_chan, vc.chan);
+}
+
+static inline struct bcm2835_desc *to_bcm2835_dma_desc(
+ struct dma_async_tx_descriptor *t)
+{
+ return container_of(t, struct bcm2835_desc, vd.tx);
+}
+
+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
+{
+ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
+ dma_free_coherent(desc->vd.tx.chan->device->dev,
+ desc->control_block_size,
+ desc->control_block_base,
+ desc->control_block_base_phys);
+ kfree(desc);
+}
+
+static int bcm2835_dma_abort(void __iomem *dma_chan_base)
+{
+ unsigned long int cs;
+ int rc = 0;
+
+ cs = readl(dma_chan_base + BCM2835_DMA_CS);
+
+ if (BCM2835_DMA_ACTIVE & cs) {
+ long int timeout = 10000;
+
+ /* write 0 to the active bit - pause the DMA */
+ writel(0, dma_chan_base + BCM2835_DMA_CS);
+
+ /* wait for any current AXI transfer to complete */
+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)
+ cs = readl(dma_chan_base + BCM2835_DMA_CS);
+
+ if (cs & BCM2835_DMA_ISPAUSED) {
+ /* we'll un-pause when we set of our next DMA */
+ rc = -ETIMEDOUT;
+
+ } else if (BCM2835_DMA_ACTIVE & cs) {
+ /* terminate the control block chain */
+ writel(0, dma_chan_base + BCM2835_DMA_NEXTCB);
+
+ /* abort the whole DMA */
+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
+ dma_chan_base + BCM2835_DMA_CS);
+ }
+ }
+
+ return rc;
+}
+
+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
+ struct bcm2835_desc *d;
+
+ if (!vd) {
+ c->desc = NULL;
+ return;
+ }
+
+ list_del(&vd->node);
+
+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
+
+ dsb(); /* ARM data synchronization (push) operation */
+
+ writel(d->control_block_base_phys, c->dma_chan_base + BCM2835_DMA_ADDR);
+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+}
+
+static irqreturn_t bcm2835_dma_callback(int irq, void *data)
+{
+ struct bcm2835_chan *c = data;
+ struct bcm2835_desc *d;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+
+ /* acknowledge interrupt */
+ writel(BCM2835_DMA_INT, c->dma_chan_base + BCM2835_DMA_CS);
+
+ d = c->desc;
+
+ if (d) {
+ if (!c->cyclic) {
+ bcm2835_dma_start_desc(c);
+ vchan_cookie_complete(&d->vd);
+ } else {
+ vchan_cyclic_callback(&d->vd);
+ }
+ }
+
+ /* keep the DMA engine running */
+ dsb(); /* ARM synchronization barrier */
+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ int ret;
+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device);
+ uint32_t chans = d->chans_available;
+ int chanID = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&d->lock, flags);
+
+ chans = d->chans_available;
+
+ dev_dbg(c->vc.chan.device->dev,
+ "allocating channel for %u\n", c->dma_sig);
+
+ /* do not use the FIQ and BULK channels */
+ chans &= ~0xD;
+
+ if (!chans) {
+ spin_unlock_irqrestore(&d->lock, flags);
+ return -ENOMEM;
+ }
+
+ /* return the ordinal of the first channel in the bitmap */
+ chanID = __ffs(chans);
+
+ /* claim the channel */
+ d->chans_available &= ~(1 << chanID);
+
+ c->dma_chan_base = BCM2835_DMA_CHANIO(d->dma_base, chanID);
+ c->dma_irq_number = d->dma_irq_numbers[chanID];
+ c->dma_ch = chanID;
+
+ ret = request_irq(c->dma_irq_number,
+ bcm2835_dma_callback, 0, "DMA IRQ", c);
+
+ spin_unlock_irqrestore(&d->lock, flags);
+
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device);
+ unsigned long flags;
+
+ spin_lock_irqsave(&d->lock, flags);
+ vchan_free_chan_resources(&c->vc);
+ d->chans_available |= 1 << c->dma_ch;
+ free_irq(c->dma_irq_number, c);
+ spin_unlock_irqrestore(&d->lock, flags);
+
+ dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
+}
+
+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
+{
+ unsigned i;
+ size_t size;
+
+ for (size = i = 0; i < d->frames; i++) {
+ struct bcm2835_dma_cb *control_block =
+ &d->control_block_base[i];
+
+ size += control_block->length;
+ }
+
+ return size;
+}
+
+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
+{
+ unsigned i;
+ size_t size;
+
+ for (size = i = 0; i < d->frames; i++) {
+ struct bcm2835_dma_cb *control_block =
+ &d->control_block_base[i];
+ size_t this_size = control_block->length;
+ dma_addr_t dma;
+
+ if (d->dir == DMA_DEV_TO_MEM)
+ dma = control_block->dst;
+ else
+ dma = control_block->src;
+
+ if (size)
+ size += this_size;
+ else if (addr >= dma && addr < dma + this_size)
+ size += dma + this_size - addr;
+ }
+
+ return size;
+}
+
+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ struct virt_dma_desc *vd;
+ enum dma_status ret;
+ unsigned long flags;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_SUCCESS || !txstate)
+ return ret;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ vd = vchan_find_desc(&c->vc, cookie);
+ if (vd) {
+ txstate->residue =
+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
+ struct bcm2835_desc *d = c->desc;
+ dma_addr_t pos;
+
+ if (d->dir == DMA_MEM_TO_DEV)
+ pos = readl(c->dma_chan_base + BCM2835_DMA_SOURCE_AD);
+ else if (d->dir == DMA_DEV_TO_MEM)
+ pos = readl(c->dma_chan_base + BCM2835_DMA_DEST_AD);
+ else
+ pos = 0;
+
+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
+ } else {
+ txstate->residue = 0;
+ }
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return ret;
+}
+
+static void bcm2835_dma_issue_pending(struct dma_chan *chan)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ unsigned long flags;
+
+ c->cyclic = true; /* nothing else is implemented */
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (vchan_issue_pending(&c->vc) && !c->desc) {
+ bcm2835_dma_start_desc(c);
+ }
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+}
+
+
+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ enum dma_slave_buswidth dev_width;
+ struct bcm2835_desc *d;
+ dma_addr_t dev_addr;
+ unsigned es, sync_type;
+ unsigned frame;
+
+ /* Grab configuration */
+ if (direction == DMA_DEV_TO_MEM) {
+ dev_addr = c->cfg.src_addr;
+ dev_width = c->cfg.src_addr_width;
+ sync_type = BCM2835_DMA_S_DREQ;
+ } else if (direction == DMA_MEM_TO_DEV) {
+ dev_addr = c->cfg.dst_addr;
+ dev_width = c->cfg.dst_addr_width;
+ sync_type = BCM2835_DMA_D_DREQ;
+ } else {
+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
+ return NULL;
+ }
+
+ /* Bus width translates to the element size (ES) */
+ switch (dev_width) {
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ es = BCM2835_DMA_DATA_TYPE_S32;
+ break;
+ default:
+ return NULL;
+ }
+
+ /* Now allocate and setup the descriptor. */
+ d = kzalloc(sizeof(*d), GFP_ATOMIC);
+ if (!d)
+ return NULL;
+
+ d->dir = direction;
+ d->dev_addr = dev_addr;
+ d->frames = buf_len / period_len;
+
+ /* Allocate memory for control blocks */
+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
+ d->control_block_base = dma_alloc_coherent(chan->device->dev,
+ d->control_block_size, &d->control_block_base_phys,
+ GFP_KERNEL);
+
+ if (!d->control_block_base) {
+ dev_err(chan->device->dev,
+ "%s: Memory allocation error\n", __func__);
+ return NULL;
+ }
+
+ memset(d->control_block_base, 0, d->control_block_size);
+
+ /*
+ * Iterate over all frames, create a control block
+ * for each frame and link them together.
+ */
+ for (frame = 0; frame < d->frames; frame++) {
+ struct bcm2835_dma_cb *control_block =
+ &d->control_block_base[frame];
+
+ /* Setup adresses */
+ if (d->dir == DMA_DEV_TO_MEM) {
+ control_block->info = BCM2835_DMA_D_INC;
+ control_block->src = d->dev_addr;
+ control_block->dst = buf_addr + frame * period_len;
+ } else {
+ control_block->info = BCM2835_DMA_S_INC;
+ control_block->src = buf_addr + frame * period_len;
+ control_block->dst = d->dev_addr;
+ }
+
+ /* Enable interrupt */
+ control_block->info |= BCM2835_DMA_INT_EN;
+
+ /* Setup synchronization */
+ if (sync_type != 0)
+ control_block->info |= sync_type;
+
+ /* Setup DREQ channel */
+ if (c->dreq != 0)
+ control_block->info |=
+ BCM2835_DMA_PER_MAP(c->dreq);
+
+ /* Length of a frame */
+ control_block->length = period_len;
+
+ /*
+ * Next block is the next frame.
+ * This DMA engine driver currently only supports cyclic DMA.
+ * Therefore, wrap around at number of frames.
+ */
+ control_block->next = d->control_block_base_phys +
+ sizeof(struct bcm2835_dma_cb) * ((frame + 1) % (d->frames));
+
+ /* The following fields are not used here */
+ control_block->stride = 0;
+ control_block->pad[0] = 0;
+ control_block->pad[1] = 0;
+ }
+
+ return vchan_tx_prep(&c->vc, &d->vd, flags);
+}
+
+static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
+ struct dma_slave_config *cfg)
+{
+ if ((cfg->direction == DMA_DEV_TO_MEM &&
+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (cfg->direction == DMA_MEM_TO_DEV &&
+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (cfg->direction != DMA_DEV_TO_MEM &&
+ cfg->direction != DMA_MEM_TO_DEV)) {
+ return -EINVAL;
+ }
+
+ c->cfg = *cfg;
+
+ return 0;
+}
+
+static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
+{
+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
+ unsigned long flags;
+ int timeout = 1000;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+
+ /* Prevent this channel being scheduled */
+ spin_lock(&d->lock);
+ list_del_init(&c->node);
+ spin_unlock(&d->lock);
+
+ /*
+ * Stop DMA activity: we assume the callback will not be called
+ * after bcm_dma_abort() returns (even if it does, it will see
+ * c->desc is NULL and exit.)
+ */
+ if (c->desc) {
+ c->desc = NULL;
+ bcm2835_dma_abort(c->dma_chan_base);
+
+ /* Wait for stopping */
+ while (timeout > 0) {
+ timeout--;
+ if(!(readl(c->dma_chan_base + BCM2835_DMA_CS) &
+ BCM2835_DMA_ACTIVE))
+ break;
+
+ cpu_relax();
+ }
+ }
+
+ vchan_get_all_descriptors(&c->vc, &head);
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+ vchan_dma_desc_free_list(&c->vc, &head);
+
+ return 0;
+}
+
+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ unsigned long arg)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ int ret;
+
+ switch (cmd) {
+ case DMA_SLAVE_CONFIG:
+ return bcm2835_dma_slave_config(c,
+ (struct dma_slave_config *)arg);
+
+ case DMA_TERMINATE_ALL:
+ bcm2835_dma_terminate_all(c);
+ break;
+
+ case DMA_PAUSE:
+ ret = -EINVAL;
+ break;
+
+ case DMA_RESUME:
+ ret = -EINVAL;
+ break;
+
+ default:
+ ret = -ENXIO;
+ break;
+ }
+
+ return ret;
+}
+
+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *od, int dma_sig)
+{
+ struct bcm2835_chan *c;
+
+ c = kzalloc(sizeof(*c), GFP_KERNEL);
+ if (!c)
+ return -ENOMEM;
+
+ c->dma_sig = dma_sig;
+ c->vc.desc_free = bcm2835_dma_desc_free;
+ vchan_init(&c->vc, &od->ddev);
+ INIT_LIST_HEAD(&c->node);
+
+ od->ddev.chancnt++;
+
+ return 0;
+}
+
+static void bcm2835_dma_free(struct bcm2835_dmadev *od)
+{
+ while (!list_empty(&od->ddev.channels)) {
+ struct bcm2835_chan *c = list_first_entry(&od->ddev.channels,
+ struct bcm2835_chan, vc.chan.device_node);
+
+ list_del(&c->vc.chan.device_node);
+ tasklet_kill(&c->vc.task);
+ kfree(c);
+ }
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id bcm2835_dma_of_match[] = {
+ {
+ .compatible = "brcm,bcm2835-dma",
+ }
+};
+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
+#endif
+
+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct bcm2835_dmadev *d = ofdma->of_dma_data;
+ struct dma_chan *chan, *candidate;
+
+retry:
+ candidate = NULL;
+
+ /* walk the list of channels registered with the current instance and
+ * find one that is currently unused */
+ list_for_each_entry(chan, &d->ddev.channels, device_node)
+ if (chan->client_count == 0) {
+ candidate = chan;
+ break;
+ }
+
+ if (!candidate)
+ return NULL;
+
+ /* dma_get_slave_channel will return NULL if we lost a race between
+ * the lookup and the reservation */
+ chan = dma_get_slave_channel(candidate);
+
+ if (chan) {
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+
+ /* Set DREQ from param */
+ c->dreq = dma_spec->args[0];
+
+ return chan;
+ }
+
+ goto retry;
+}
+
+static int bcm2835_dma_probe(struct platform_device *pdev)
+{
+ struct bcm2835_dmadev *od;
+ struct resource *dma_res = NULL;
+ void __iomem *dma_base = NULL;
+ int rc = 0;
+ int i;
+ struct resource *irq;
+ int irq_resources;
+
+ if (!pdev->dev.dma_mask)
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (rc)
+ return rc;
+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
+ if (!od)
+ return -ENOMEM;
+
+ pdev->dev.dma_parms = &od->dma_parms;
+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
+
+ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dma_base = devm_ioremap_resource(&pdev->dev, dma_res);
+ if (IS_ERR(dma_base))
+ return PTR_ERR(dma_base);
+
+ od->dma_base = dma_base;
+
+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
+ od->ddev.device_control = bcm2835_dma_control;
+ od->ddev.dev = &pdev->dev;
+ INIT_LIST_HEAD(&od->ddev.channels);
+ spin_lock_init(&od->lock);
+
+ irq_resources = 0;
+
+ for (i = 0; i < pdev->num_resources; i++) {
+ if (platform_get_resource(pdev, IORESOURCE_IRQ, i) > 0)
+ irq_resources++;
+ }
+
+ od->dma_irq_numbers = devm_kzalloc(&pdev->dev,
+ irq_resources*sizeof(int), GFP_KERNEL);
+ if (!od)
+ return -ENOMEM;
+
+ for (i = 0; i < irq_resources; i++) {
+ rc = bcm2835_dma_chan_init(od, i);
+ if (rc) {
+ bcm2835_dma_free(od);
+ return rc;
+ }
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!irq) {
+ dev_err(&pdev->dev,
+ "No IRQ resource for channel %i\n", i);
+ return -ENODEV;
+ }
+ od->dma_irq_numbers[i] = irq->start;
+ }
+
+ rc = dma_async_device_register(&od->ddev);
+ if (rc) {
+ dev_err(&pdev->dev,
+ "Failed to register slave DMA engine device: %d\n", rc);
+ bcm2835_dma_free(od);
+ return rc;
+ }
+
+ platform_set_drvdata(pdev, od);
+
+ if (pdev->dev.of_node) {
+ const void *chan_mask;
+
+ /* Device-tree DMA controller registration */
+ rc = of_dma_controller_register(pdev->dev.of_node,
+ bcm2835_dma_xlate, od);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed to register DMA controller\n");
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+ return rc;
+ }
+
+ /* Request DMA channel mask from device tree */
+ chan_mask = of_get_property(pdev->dev.of_node,
+ "dma-channel-mask", NULL);
+
+ if (!chan_mask) {
+ dev_err(&pdev->dev, "Failed to get channel mask\n");
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+ return -EINVAL;
+ }
+
+ od->chans_available = be32_to_cpup(chan_mask);
+ }
+
+ dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
+
+ return rc;
+}
+
+static int bcm2835_dma_remove(struct platform_device *pdev)
+{
+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
+
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+
+ return 0;
+}
+
+static struct platform_driver bcm2835_dma_driver = {
+ .probe = bcm2835_dma_probe,
+ .remove = bcm2835_dma_remove,
+ .driver = {
+ .name = "bcm2835-dma",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
+ },
+};
+
+module_platform_driver(bcm2835_dma_driver);
+
+MODULE_AUTHOR("Florian Meier");
+MODULE_DESCRIPTION("BCM2835 DMA engine driver");
+MODULE_LICENSE("GPL");
+
--
1.7.9.5
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[Russell King - ARM Linux]

On Mon, Nov 11, 2013 at 11:05:21PM +0100, Florian Meier wrote:
> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.
>
> Signed-off-by: Florian Meier <floria...@koalo.de>
> ---
>
> Thank you for your comments!
> I hope I have now removed all leftovers of the sg struct.
> Regarding the endian-ness: I have not found any hint about that in the
> datasheet. Therefore, I chose uint32_t. If you think fixed le32 is more
> likely I will change it.

I guess it's easy to change later if needed; there's likely a large
number of drivers which fall into this same category.

> The PAD fields do not seem to be used, but the datasheet states they
> should be set to 0.

Ok. This now looks a lot better, and is smaller too! There's a few
issues which need to be resolved still...

> +struct bcm2835_desc {
> + struct virt_dma_desc vd;
> + enum dma_transfer_direction dir;
> + dma_addr_t dev_addr;

I don't think you need dev_addr here anymore - it seems to only be used
within bcm2835_dma_prep_dma_cyclic().

> +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
> +{
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> + int ret;
> + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device);
> + uint32_t chans = d->chans_available;

Probably just uint32_t chans; here is sufficient. Also, as you'll be
touching this area again, a minor comment to order the variable
declarations in a more tidy way here.

> + int chanID = 0;

Is a channel ID of zero a legal channel number?

Calling request_irq() from within a spinlocked region is not a nice thing
to do. May I suggest an alternative coding for this function?

int chanID = -1;

dev_dbg(c->vc.chan.device->dev,

"allocating channel for %u\n", c->dma_sig);

spin_lock_irqsave(&d->lock, flags);

chans = d->chans_available;
if (chans) {

/* return the ordinal of the first channel in the bitmap */

chanID = __ffs(chans);

d->chans_available &= ~(1 << chanID);
}

spin_unlock_irqrestore(&d->lock, flags);

if (chanID == -1)
return -ENOMEM;

c->dma_chan_base = BCM2835_DMA_CHANIO(d->dma_base, chanID);

c->dma_irq_number = d->dma_irq_numbers[chanID];

c->dma_ch = chanID;

ret = request_irq(c->dma_irq_number,

bcm2835_dma_callback, 0, "DMA IRQ", c);

Now, don't forget to clean up if request_irq() fails...

if (ret < 0) {
spin_lock_irqsave(&d->lock, flags);
d->chans_available |= 1 << chanID;
spin_unlock_irqrestore(&d->lock, flags);
}

return ret;

How does that look?

> +
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
> +{
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&d->lock, flags);
> + vchan_free_chan_resources(&c->vc);
> + d->chans_available |= 1 << c->dma_ch;
> + free_irq(c->dma_irq_number, c);
> + spin_unlock_irqrestore(&d->lock, flags);

A better ordering here would be:

vchan_free_chan_resources(&c->vc);
free_irq(c->dma_irq_number, c);

spin_lock_irqsave(&d->lock, flags);

d->chans_available |= 1 << c->dma_ch;

spin_unlock_irqrestore(&d->lock, flags);

You don't need to call the first two under the spinlock - all you need to
protect is the read-modify-write of d->chans_available here and also in
the above function.

...

> + /*
> + * Next block is the next frame.
> + * This DMA engine driver currently only supports cyclic DMA.
> + * Therefore, wrap around at number of frames.
> + */
> + control_block->next = d->control_block_base_phys +
> + sizeof(struct bcm2835_dma_cb) * ((frame + 1) % (d->frames));

Minor comment here - the parens around d->frames isn't required, and
wrapping this a little better would be nice. I'd suggest moving
((frame + 1) % d->frames) onto the next line.

Other than those comments, it's looking really quite good! Well done.

[Vinod Koul]

On Mon, Nov 11, 2013 at 11:05:21PM +0100, Florian Meier wrote:

> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.
>
> Signed-off-by: Florian Meier <floria...@koalo.de>
> ---
>
> Thank you for your comments!
> I hope I have now removed all leftovers of the sg struct.
> Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I chose uint32_t. If you think fixed le32 is more likely I will change it.
> The PAD fields do not seem to be used, but the datasheet states they should be set to 0.

can you pls reflow this to 80chars...

Also going thru driver I suspect you have not run checkpatch, pls do run this
scriprt to check for coding style

> +static irqreturn_t bcm2835_dma_callback(int irq, void *data)
> +{
> + struct bcm2835_chan *c = data;
> + struct bcm2835_desc *d;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> +
> + /* acknowledge interrupt */
> + writel(BCM2835_DMA_INT, c->dma_chan_base + BCM2835_DMA_CS);
> +
> + d = c->desc;
> +
> + if (d) {
> + if (!c->cyclic) {
> + bcm2835_dma_start_desc(c);
> + vchan_cookie_complete(&d->vd);

I dont see callback being invoked for this case?

> + } else {
> + vchan_cyclic_callback(&d->vd);
> + }
> + }
> +
> + /* keep the DMA engine running */
> + dsb(); /* ARM synchronization barrier */
> + writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
> +
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
> +{
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> + int ret;
> + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(chan->device);
> + uint32_t chans = d->chans_available;
> + int chanID = 0;

Pls avoid camel case

unconditional return ret; will do same!

> +static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
> +{
> + unsigned i;
> + size_t size;
> +
> + for (size = i = 0; i < d->frames; i++) {
> + struct bcm2835_dma_cb *control_block =
> + &d->control_block_base[i];
> +
> + size += control_block->length;
> + }
> +
> + return size;

you may want to store this in descritpor which creating that, so you can
avoid computation at query

GFP_NOWAIT is recommendation for DMA drivers

> + if (!d)
> + return NULL;
> +
> + d->dir = direction;
> + d->dev_addr = dev_addr;
> + d->frames = buf_len / period_len;
> +
> + /* Allocate memory for control blocks */
> + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
> + d->control_block_base = dma_alloc_coherent(chan->device->dev,
> + d->control_block_size, &d->control_block_base_phys,
> + GFP_KERNEL);

ditto

> +
> + if (!d->control_block_base) {
> + dev_err(chan->device->dev,
> + "%s: Memory allocation error\n", __func__);
> + return NULL;

you need to free "d" allocated above..

> + }
> +
> + memset(d->control_block_base, 0, d->control_block_size);

you should do same for PAUSE/RESUME, actually no need to add code for those and
fall thru default!

Also since you are going to use for audio pls do implement the capablity APIs in
the driver so that thing like what you support and parametsr and automatically
discovered and need not be hard coded

> +static int bcm2835_dma_probe(struct platform_device *pdev)
> +{
> + struct bcm2835_dmadev *od;
> + struct resource *dma_res = NULL;
> + void __iomem *dma_base = NULL;
> + int rc = 0;
> + int i;
> + struct resource *irq;
> + int irq_resources;
> +
> + if (!pdev->dev.dma_mask)
> + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
> +
> + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
> + if (rc)
> + return rc;
> + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
> +
> + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
> + if (!od)
> + return -ENOMEM;
> +
> + pdev->dev.dma_parms = &od->dma_parms;
> + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);

Can you support such a large txn or you want to do this thur SW?

> +module_platform_driver(bcm2835_dma_driver);
> +
> +MODULE_AUTHOR("Florian Meier");
> +MODULE_DESCRIPTION("BCM2835 DMA engine driver");
> +MODULE_LICENSE("GPL");

MODULE_ALIAS too pls

--
~Vinod

[Kumar Gala]

Can you be more specific about what you mean by ‘all DMA interrupts’?

> +- #dma-cells: Must be <1>, used to represent the number of integer cells in
> +the dmas property of client devices.
> +- dma-channels: Maximum number of DMA channels available
> +- dma-requests: Number of DMA Requests.
> +- dma-channel-mask: Bit mask representing the channels available.

Should be brcm,dma-channel-mask

- k

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

[Florian Meier]

Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
Currently it only supports cyclic DMA.

Signed-off-by: Florian Meier <floria...@koalo.de>
---

Besides of many minor improvements (thanks to your helpful comments),
this fourth version does the assignment of the virtual to the hardware
channel already in probe. This simplifies things a lot
(first of all the complex alloc_chan_resources is now gone).

Regarding the maximum segment size: 0x3FFFFFFF is the maximum possible
DMA transfer length value and I have no evidence that the maximum
segment size is smaller.

.../devicetree/bindings/dma/bcm2835-dma.txt | 59 ++

drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +

drivers/dma/bcm2835-dma.c | 750 ++++++++++++++++++++
4 files changed, 816 insertions(+)

create mode 100644 Documentation/devicetree/bindings/dma/bcm2835-dma.txt
create mode 100644 drivers/dma/bcm2835-dma.c

diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
new file mode 100644

index 0000000..bca5e84
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
@@ -0,0 +1,59 @@

+* BCM2835 DMA controller
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-dma".
+- reg: Should contain DMA registers location and length.

+- interrupts: Should contain the DMA interrupts associated
+ to the DMA channels in ascending order.
+ First cell is the IRQ bank.

+ Second cell is the IRQ number.

+- #dma-cells: Must be <1>, used to represent the number of integer cells in

+ the dmas property of client devices.
+- dma-channels: Maximum number of DMA channels available.

+- dma-requests: Number of DMA Requests.

+- brcm,dma-channel-mask: Bit mask representing the channels available.

+
+Example:
+
+dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16
+ 1 17
+ 1 18
+ 1 19
+ 1 20
+ 1 21
+ 1 22
+ 1 23
+ 1 24
+ 1 25
+ 1 26
+ 1 27
+ 1 28>;
+
+ #dma-cells = <1>;

+ dma-channels = <16>;
+ dma-requests = <32>;
+ brcm,dma-channel-mask = <0x7f35>;

+};
+
+DMA clients connected to the BCM2835 DMA controller must use the format
+described in the dma.txt file, using a two-cell specifier for each channel:
+a phandle plus one integer cells.
+The two cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. The DREQ number.
+
+Example:
+
+bcm2835_i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+ reg = < 0x7e203000 0x20
+ 0x7e101098 0x02>;
+
+ dmas = <&dma 2
+ &dma 3>;
+ dma-names = "tx", "rx";
+};

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index c61a6ec..880e723 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -300,6 +300,12 @@ config DMA_OMAP

select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS

+config DMA_BCM2835
+ tristate "BCM2835 DMA engine support"
+ depends on (ARCH_BCM2835 || MACH_BCM2708)
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+
config TI_CPPI41
tristate "AM33xx CPPI41 DMA support"
depends on ARCH_OMAP
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile

index 0ce2da9..0a6f08e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o

obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
+obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c

new file mode 100644
index 0000000..baf072e
--- /dev/null
+++ b/drivers/dma/bcm2835-dma.c
@@ -0,0 +1,750 @@

+ */
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+
+#include "virt-dma.h"
+
+struct bcm2835_dmadev {
+ struct dma_device ddev;
+ spinlock_t lock;

+ void __iomem *dma_base;

+ struct device_dma_parameters dma_parms;
+};
+
+struct bcm2835_dma_cb {
+ uint32_t info;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t length;
+ uint32_t stride;
+ uint32_t next;
+ uint32_t pad[2];
+};
+
+struct bcm2835_chan {
+ struct virt_dma_chan vc;
+ struct list_head node;
+
+ struct dma_slave_config cfg;

+ bool cyclic;
+ unsigned dreq;
+
+ int dma_ch;
+ struct bcm2835_desc *desc;
+
+ void __iomem *dma_chan_base;
+ int dma_irq_number;
+};
+

+struct bcm2835_desc {
+ struct virt_dma_desc vd;
+ enum dma_transfer_direction dir;
+

+ unsigned int control_block_size;
+ struct bcm2835_dma_cb *control_block_base;
+ dma_addr_t control_block_base_phys;
+
+ unsigned frames;

+ size_t size;
+};
+

+ int rc = 0;
+

+ cs = readl(dma_chan_base + BCM2835_DMA_CS);
+
+ if (BCM2835_DMA_ACTIVE & cs) {
+ long int timeout = 10000;
+
+ /* write 0 to the active bit - pause the DMA */

+ writel(0, dma_chan_base + BCM2835_DMA_CS);
+

+ /* wait for any current AXI transfer to complete */
+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)
+ cs = readl(dma_chan_base + BCM2835_DMA_CS);
+
+ if (cs & BCM2835_DMA_ISPAUSED) {
+ /* we'll un-pause when we set of our next DMA */
+ rc = -ETIMEDOUT;
+
+ } else if (BCM2835_DMA_ACTIVE & cs) {
+ /* terminate the control block chain */
+ writel(0, dma_chan_base + BCM2835_DMA_NEXTCB);
+
+ /* abort the whole DMA */
+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,

+ dma_chan_base + BCM2835_DMA_CS);
+ }
+ }

+
+ return rc;
+}
+
+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);

+ struct bcm2835_desc *d;
+

+ if (!vd) {
+ c->desc = NULL;
+ return;
+ }
+
+ list_del(&vd->node);
+
+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
+
+ dsb(); /* ARM data synchronization (push) operation */
+
+ writel(d->control_block_base_phys, c->dma_chan_base + BCM2835_DMA_ADDR);

+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+}
+

+static irqreturn_t bcm2835_dma_callback(int irq, void *data)
+{
+ struct bcm2835_chan *c = data;
+ struct bcm2835_desc *d;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+
+ /* acknowledge interrupt */
+ writel(BCM2835_DMA_INT, c->dma_chan_base + BCM2835_DMA_CS);
+
+ d = c->desc;
+
+ if (d) {

+ /* TODO Only works for cyclic DMA */

+ vchan_cyclic_callback(&d->vd);
+ }
+
+ /* keep the DMA engine running */
+ dsb(); /* ARM synchronization barrier */
+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+

+ dev_dbg(c->vc.chan.device->dev,
+ "Allocating DMA channel %i\n", c->dma_ch);
+
+ return request_irq(c->dma_irq_number,

+ bcm2835_dma_callback, 0, "DMA IRQ", c);
+}
+

+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)

+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+

+ vchan_free_chan_resources(&c->vc);
+ free_irq(c->dma_irq_number, c);
+
+ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->dma_ch);
+}
+

+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
+{

+ return d->size;

+}
+
+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)

+{
+ unsigned i;
+ size_t size;
+
+ for (size = i = 0; i < d->frames; i++) {
+ struct bcm2835_dma_cb *control_block =
+ &d->control_block_base[i];

+ size_t this_size = control_block->length;
+ dma_addr_t dma;
+
+ if (d->dir == DMA_DEV_TO_MEM)
+ dma = control_block->dst;
+ else
+ dma = control_block->src;
+
+ if (size)
+ size += this_size;
+ else if (addr >= dma && addr < dma + this_size)
+ size += dma + this_size - addr;

+ }
+
+ return size;

+}
+
+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)

+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);

+ struct virt_dma_desc *vd;
+ enum dma_status ret;

+ unsigned long flags;
+

+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_SUCCESS || !txstate)

+ return ret;
+

+ spin_lock_irqsave(&c->vc.lock, flags);
+ vd = vchan_find_desc(&c->vc, cookie);
+ if (vd) {
+ txstate->residue =
+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
+ struct bcm2835_desc *d = c->desc;
+ dma_addr_t pos;
+
+ if (d->dir == DMA_MEM_TO_DEV)
+ pos = readl(c->dma_chan_base + BCM2835_DMA_SOURCE_AD);
+ else if (d->dir == DMA_DEV_TO_MEM)
+ pos = readl(c->dma_chan_base + BCM2835_DMA_DEST_AD);
+ else
+ pos = 0;
+
+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
+ } else {
+ txstate->residue = 0;
+ }

+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+

+ return ret;
+}
+

+static void bcm2835_dma_issue_pending(struct dma_chan *chan)

+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);

+ unsigned long flags;
+

+ c->cyclic = true; /* nothing else is implemented */

+
+ spin_lock_irqsave(&c->vc.lock, flags);

+ if (vchan_issue_pending(&c->vc) && !c->desc)
+ bcm2835_dma_start_desc(c);

+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+}
+

+

+ d = kzalloc(sizeof(*d), GFP_NOWAIT);

+ if (!d)
+ return NULL;
+
+ d->dir = direction;

+ d->frames = buf_len / period_len;
+
+ /* Allocate memory for control blocks */
+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
+ d->control_block_base = dma_alloc_coherent(chan->device->dev,
+ d->control_block_size, &d->control_block_base_phys,

+ GFP_NOWAIT);

+
+ if (!d->control_block_base) {

+ kfree(d);

+ dev_err(chan->device->dev,
+ "%s: Memory allocation error\n", __func__);
+ return NULL;

+ }
+
+ memset(d->control_block_base, 0, d->control_block_size);

+
+ /*
+ * Iterate over all frames, create a control block
+ * for each frame and link them together.
+ */
+ for (frame = 0; frame < d->frames; frame++) {

+ struct bcm2835_dma_cb *control_block =

+ &d->control_block_base[frame];
+
+ /* Setup adresses */
+ if (d->dir == DMA_DEV_TO_MEM) {
+ control_block->info = BCM2835_DMA_D_INC;

+ control_block->src = dev_addr;

+ control_block->dst = buf_addr + frame * period_len;
+ } else {
+ control_block->info = BCM2835_DMA_S_INC;
+ control_block->src = buf_addr + frame * period_len;

+ control_block->dst = dev_addr;

+ }
+
+ /* Enable interrupt */
+ control_block->info |= BCM2835_DMA_INT_EN;
+
+ /* Setup synchronization */
+ if (sync_type != 0)
+ control_block->info |= sync_type;
+
+ /* Setup DREQ channel */
+ if (c->dreq != 0)
+ control_block->info |=
+ BCM2835_DMA_PER_MAP(c->dreq);
+
+ /* Length of a frame */
+ control_block->length = period_len;

+ d->size += control_block->length;
+

+ /*
+ * Next block is the next frame.
+ * This DMA engine driver currently only supports cyclic DMA.
+ * Therefore, wrap around at number of frames.
+ */
+ control_block->next = d->control_block_base_phys +
+ sizeof(struct bcm2835_dma_cb)

+ * ((frame + 1) % d->frames);

+
+ /* The following fields are not used here */
+ control_block->stride = 0;
+ control_block->pad[0] = 0;
+ control_block->pad[1] = 0;
+ }
+
+ return vchan_tx_prep(&c->vc, &d->vd, flags);
+}
+
+static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
+ struct dma_slave_config *cfg)
+{
+ if ((cfg->direction == DMA_DEV_TO_MEM &&
+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (cfg->direction == DMA_MEM_TO_DEV &&
+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (cfg->direction != DMA_DEV_TO_MEM &&
+ cfg->direction != DMA_MEM_TO_DEV)) {
+ return -EINVAL;
+ }
+
+ c->cfg = *cfg;

+
+ return 0;
+}
+

+static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
+{

+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
+ unsigned long flags;

+ int timeout = 1000;
+ LIST_HEAD(head);

+
+ spin_lock_irqsave(&c->vc.lock, flags);
+

+ /* Prevent this channel being scheduled */
+ spin_lock(&d->lock);
+ list_del_init(&c->node);
+ spin_unlock(&d->lock);
+
+ /*
+ * Stop DMA activity: we assume the callback will not be called
+ * after bcm_dma_abort() returns (even if it does, it will see
+ * c->desc is NULL and exit.)
+ */
+ if (c->desc) {
+ c->desc = NULL;
+ bcm2835_dma_abort(c->dma_chan_base);
+
+ /* Wait for stopping */
+ while (timeout > 0) {
+ timeout--;

+ if (!(readl(c->dma_chan_base + BCM2835_DMA_CS) &

+ BCM2835_DMA_ACTIVE))
+ break;
+
+ cpu_relax();
+ }
+

+ if (timeout <= 0)
+ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");

+ }
+
+ vchan_get_all_descriptors(&c->vc, &head);

+ spin_unlock_irqrestore(&c->vc.lock, flags);
+ vchan_dma_desc_free_list(&c->vc, &head);

+
+ return 0;
+}
+

+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ unsigned long arg)
+{
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ int ret;
+
+ switch (cmd) {
+ case DMA_SLAVE_CONFIG:
+ return bcm2835_dma_slave_config(c,
+ (struct dma_slave_config *)arg);
+
+ case DMA_TERMINATE_ALL:
+ bcm2835_dma_terminate_all(c);
+ break;
+

+ default:
+ ret = -ENXIO;
+ break;

+ }
+

+ return ret;
+}
+

+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
+{

+ struct bcm2835_chan *c;
+
+ c = kzalloc(sizeof(*c), GFP_KERNEL);
+ if (!c)

+ return -ENOMEM;
+

+ c->vc.desc_free = bcm2835_dma_desc_free;

+ vchan_init(&c->vc, &d->ddev);
+ INIT_LIST_HEAD(&c->node);
+
+ d->ddev.chancnt++;
+
+ c->dma_chan_base = BCM2835_DMA_CHANIO(d->dma_base, chan_id);
+ c->dma_ch = chan_id;
+ c->dma_irq_number = irq;

+
+ return 0;
+}
+

+static void bcm2835_dma_free(struct bcm2835_dmadev *od)
+{
+ while (!list_empty(&od->ddev.channels)) {
+ struct bcm2835_chan *c = list_first_entry(&od->ddev.channels,
+ struct bcm2835_chan, vc.chan.device_node);
+
+ list_del(&c->vc.chan.device_node);
+ tasklet_kill(&c->vc.task);
+ kfree(c);
+ }
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id bcm2835_dma_of_match[] = {

+ { .compatible = "brcm,bcm2835-dma", },
+ {},

+};
+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
+#endif
+
+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct bcm2835_dmadev *d = ofdma->of_dma_data;
+ struct dma_chan *chan, *candidate;
+
+retry:
+ candidate = NULL;
+
+ /* walk the list of channels registered with the current instance and
+ * find one that is currently unused */
+ list_for_each_entry(chan, &d->ddev.channels, device_node)
+ if (chan->client_count == 0) {
+ candidate = chan;
+ break;
+ }
+
+ if (!candidate)

+ return NULL;
+

+ /* dma_get_slave_channel will return NULL if we lost a race between
+ * the lookup and the reservation */
+ chan = dma_get_slave_channel(candidate);
+
+ if (chan) {

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+

+ /* Set DREQ from param */
+ c->dreq = dma_spec->args[0];
+
+ return chan;
+ }
+
+ goto retry;
+}
+

+static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
+ struct dma_slave_caps *caps)
+{
+ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ caps->cmd_pause = false;
+ caps->cmd_terminate = true;

+
+ return 0;
+}
+

+static int bcm2835_dma_probe(struct platform_device *pdev)
+{
+ struct bcm2835_dmadev *od;
+ struct resource *dma_res = NULL;
+ void __iomem *dma_base = NULL;
+ int rc = 0;

+ int i = 0;
+ int irq;
+ uint32_t chans_available;

+
+ if (!pdev->dev.dma_mask)
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (rc)
+ return rc;
+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
+ if (!od)
+ return -ENOMEM;
+
+ pdev->dev.dma_parms = &od->dma_parms;
+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);

+
+ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dma_base = devm_ioremap_resource(&pdev->dev, dma_res);
+ if (IS_ERR(dma_base))
+ return PTR_ERR(dma_base);
+
+ od->dma_base = dma_base;
+
+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;

+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;

+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
+ od->ddev.device_control = bcm2835_dma_control;
+ od->ddev.dev = &pdev->dev;
+ INIT_LIST_HEAD(&od->ddev.channels);
+ spin_lock_init(&od->lock);
+

+ platform_set_drvdata(pdev, od);
+
+ if (pdev->dev.of_node) {
+ const void *chan_mask;
+
+ /* Device-tree DMA controller registration */
+ rc = of_dma_controller_register(pdev->dev.of_node,
+ bcm2835_dma_xlate, od);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed to register DMA controller\n");
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+ return rc;
+ }
+
+ /* Request DMA channel mask from device tree */
+ chan_mask = of_get_property(pdev->dev.of_node,

+ "brcm,dma-channel-mask", NULL);

+
+ if (!chan_mask) {
+ dev_err(&pdev->dev, "Failed to get channel mask\n");
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+ return -EINVAL;
+ }
+

+ chans_available = be32_to_cpup(chan_mask);

+
+ /* do not use the FIQ and BULK channels */

+ chans_available &= ~0xD;

+
+ for (i = 0; i < pdev->num_resources; i++) {

+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ break;
+
+ if (chans_available & (1 << i)) {
+ rc = bcm2835_dma_chan_init(od, i, irq);

+ if (rc) {
+ bcm2835_dma_free(od);
+ return rc;
+ }
+ }
+ }

+ }
+
+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);

+
+ rc = dma_async_device_register(&od->ddev);
+ if (rc) {
+ dev_err(&pdev->dev,
+ "Failed to register slave DMA engine device: %d\n", rc);
+ bcm2835_dma_free(od);
+ return rc;
+ }
+

+ dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
+
+ return rc;
+}
+

+static int bcm2835_dma_remove(struct platform_device *pdev)
+{

+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
+
+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);

+
+ return 0;
+}
+

+static struct platform_driver bcm2835_dma_driver = {
+ .probe = bcm2835_dma_probe,
+ .remove = bcm2835_dma_remove,
+ .driver = {
+ .name = "bcm2835-dma",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
+ },
+};
+
+module_platform_driver(bcm2835_dma_driver);
+

+MODULE_ALIAS("platform:bcm2835-dma");

+MODULE_DESCRIPTION("BCM2835 DMA engine driver");

+MODULE_AUTHOR("Florian Meier <floria...@koalo.de>");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5

[Tomasz Figa]

Hi Florian,

Seems like I accidentally replied to some old version of this patch.
Not sure how many of those comments were still relevant for V3, but
let me look at this version and see whether we can still improve things
a bit. Please see my comments inline.

The two properties above do not seem to be used anywhere in the driver.

> +- brcm,dma-channel-mask: Bit mask representing the channels available.

What does the value of this property depend on? Could you describe the
structure of this DMA controller?

> +
> +Example:
> +
> +dma: dma@7e007000 {
> + compatible = "brcm,bcm2835-dma";
> + reg = <0x7e007000 0xf00>;
> + interrupts = <1 16
> + 1 17
> + 1 18
> + 1 19
> + 1 20
> + 1 21
> + 1 22
> + 1 23
> + 1 24
> + 1 25
> + 1 26
> + 1 27
> + 1 28>;

There are 13 interrupts specified here, but...

> +
> + #dma-cells = <1>;
> + dma-channels = <16>;

...16 channels here...

> + dma-requests = <32>;
> + brcm,dma-channel-mask = <0x7f35>;

...and 11 set bits here. May I ask you to explain this to me, please?

[snip]

> diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
> new file mode 100644
> index 0000000..baf072e
> --- /dev/null
> +++ b/drivers/dma/bcm2835-dma.c

[snip]

> +static int bcm2835_dma_probe(struct platform_device *pdev)
> +{
> + struct bcm2835_dmadev *od;
> + struct resource *dma_res = NULL;
> + void __iomem *dma_base = NULL;
> + int rc = 0;
> + int i = 0;
> + int irq;
> + uint32_t chans_available;

[snip]
> + if (pdev->dev.of_node) {

Is this driver supposed to support non-DT based instantation (aka board
files)? If not, maybe it would be cleaner to simply check for
!pdev->dev.of_node at the beginning of probe and return an error?

> + const void *chan_mask;
> +
> + /* Device-tree DMA controller registration */
> + rc = of_dma_controller_register(pdev->dev.of_node,
> + bcm2835_dma_xlate, od);
> + if (rc) {
> + dev_err(&pdev->dev, "Failed to register DMA controller\n");
> + dma_async_device_unregister(&od->ddev);
> + bcm2835_dma_free(od);
> + return rc;
> + }
> +
> + /* Request DMA channel mask from device tree */
> + chan_mask = of_get_property(pdev->dev.of_node,
> + "brcm,dma-channel-mask", NULL);
> +
> + if (!chan_mask) {
> + dev_err(&pdev->dev, "Failed to get channel mask\n");
> + dma_async_device_unregister(&od->ddev);
> + bcm2835_dma_free(od);
> + return -EINVAL;
> + }
> +
> + chans_available = be32_to_cpup(chan_mask);

You can use of_property_read_u32(), which will do both of_get_property()
and be32_to_cpup() for you.

> +
> + /* do not use the FIQ and BULK channels */
> + chans_available &= ~0xD;

I'm clearly lacking the information about hardware here, but it would be
nice to hear what these channels are.

Otherwise, the driver looks pretty good.

Best regards,
Tomasz

[Florian Meier]

On 13.11.2013 19:43, Tomasz Figa wrote:
> Hi Florian,
>
> Seems like I accidentally replied to some old version of this patch.
> Not sure how many of those comments were still relevant for V3, but
> let me look at this version and see whether we can still improve things
> a bit. Please see my comments inline.

Some were still helpful (especially the idea to use the chan_init
function for setting the irq), thanks.

>> ....

>> diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
>> new file mode 100644
>> index 0000000..bca5e84
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
>> @@ -0,0 +1,59 @@
>> +* BCM2835 DMA controller
>> +
>> +Required properties:
>> +- compatible: Should be "brcm,bcm2835-dma".
>> +- reg: Should contain DMA registers location and length.
>> +- interrupts: Should contain the DMA interrupts associated
>> + to the DMA channels in ascending order.
>> + First cell is the IRQ bank.
>> + Second cell is the IRQ number.
>> +- #dma-cells: Must be <1>, used to represent the number of integer cells in
>> + the dmas property of client devices.
>> +- dma-channels: Maximum number of DMA channels available.
>> +- dma-requests: Number of DMA Requests.
>
> The two properties above do not seem to be used anywhere in the driver.

Aren't they necessary for the DMA engine core?

How I understand this DMA controller:
There are 16 DMA channels in the DMA controller, but only 13 interrupts
are available at the IRQ controller. Therefore, the upper DMA channels
can just not be used. Maybe because there are to many other IRQs and
they didn't want to implement another IRQ bank.
Furthermore, some of the DMA channels are already used by the
VideoCore/GPU/firmware. This is what dma-channel-mask indicates. This
should be automatically set by the firmware in the future.
Finally, there are some channels with special functionality that should
not be used by DMA engine, too. Therefore, these lines:

/* do not use the FIQ and BULK channels */

chans_available &= ~0xD;

> [snip]
>> diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
>> new file mode 100644
>> index 0000000..baf072e
>> --- /dev/null
>> +++ b/drivers/dma/bcm2835-dma.c
> [snip]
>> +static int bcm2835_dma_probe(struct platform_device *pdev)
>> +{
>> + struct bcm2835_dmadev *od;
>> + struct resource *dma_res = NULL;
>> + void __iomem *dma_base = NULL;
>> + int rc = 0;
>> + int i = 0;
>> + int irq;
>> + uint32_t chans_available;
> [snip]
>> + if (pdev->dev.of_node) {
>
> Is this driver supposed to support non-DT based instantation (aka board
> files)? If not, maybe it would be cleaner to simply check for
> !pdev->dev.of_node at the beginning of probe and return an error?

I would like to maintain the possibility for board file based
instatiation, because the Raspberry Pi downstream kernel still doesn't
support device tree. If this is a no-go, I will accept that.

Greetings,
Florian

[Tomasz Figa]

On Wednesday 13 of November 2013 20:35:22 Florian Meier wrote:
> On 13.11.2013 19:43, Tomasz Figa wrote:
> > Hi Florian,
> >
> > Seems like I accidentally replied to some old version of this patch.
> > Not sure how many of those comments were still relevant for V3, but
> > let me look at this version and see whether we can still improve things
> > a bit. Please see my comments inline.
>
> Some were still helpful (especially the idea to use the chan_init
> function for setting the irq), thanks.

Good. You're welcome.

>
> >> ....
> >> diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
> >> new file mode 100644
> >> index 0000000..bca5e84
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
> >> @@ -0,0 +1,59 @@
> >> +* BCM2835 DMA controller
> >> +
> >> +Required properties:
> >> +- compatible: Should be "brcm,bcm2835-dma".
> >> +- reg: Should contain DMA registers location and length.
> >> +- interrupts: Should contain the DMA interrupts associated
> >> + to the DMA channels in ascending order.
> >> + First cell is the IRQ bank.
> >> + Second cell is the IRQ number.
> >> +- #dma-cells: Must be <1>, used to represent the number of integer cells in
> >> + the dmas property of client devices.
> >> +- dma-channels: Maximum number of DMA channels available.
> >> +- dma-requests: Number of DMA Requests.
> >
> > The two properties above do not seem to be used anywhere in the driver.
>
> Aren't they necessary for the DMA engine core?

Honestly, looking at the DMA bindings documentation, these two are quite
a mystery for me. They don't seem to be used in DMA engine core, but
instead several drivers use them for private purposes.

So, since they are optional and you don't seem to need them, I wouldn't
list them.

OK, this makes it much more clear.

So, my only comment remaining here is that you shouldn't include the
channels without interrupt signal in the mask. This would allow you
to define it as a mask of channels that are operable and then just
iterate over all set bits in the driver, instead of using tricks with
interrupt resources. What do you think?

>
> > [snip]
> >> diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
> >> new file mode 100644
> >> index 0000000..baf072e
> >> --- /dev/null
> >> +++ b/drivers/dma/bcm2835-dma.c
> > [snip]
> >> +static int bcm2835_dma_probe(struct platform_device *pdev)
> >> +{
> >> + struct bcm2835_dmadev *od;
> >> + struct resource *dma_res = NULL;
> >> + void __iomem *dma_base = NULL;
> >> + int rc = 0;
> >> + int i = 0;
> >> + int irq;
> >> + uint32_t chans_available;
> > [snip]
> >> + if (pdev->dev.of_node) {
> >
> > Is this driver supposed to support non-DT based instantation (aka board
> > files)? If not, maybe it would be cleaner to simply check for
> > !pdev->dev.of_node at the beginning of probe and return an error?
>
> I would like to maintain the possibility for board file based
> instatiation, because the Raspberry Pi downstream kernel still doesn't
> support device tree. If this is a no-go, I will accept that.

Sure, you are free to do so.

What I meant is that your probe won't call bcm2835_dma_chan_init() at all
if there is no pdev->dev.of_node, because the loop iterating over channels
is under the if clause.

Best regards,
Tomasz

[Florian Meier]

Ok

Since the mask will come directly from the firmware, this would require
patching the firmware. I think that is not worth the effort.

Yes you are right, but I think it will make the patching easier, later.
Currently, nothing bad happens without device tree - it just allocates
no channels.

Greetings,
Florian

[Tomasz Figa]

Now I'm slightly confused. Do you already have code in your firmware that
adds this property to your device tree?

Otherwise in what circumstances such patching would take place? On given
hardware (unless it's an FPGA) the configuration of available DMA channels
that have interrupt signals should not change.

But isn't it really an error condition, if no channels are allocated?

Anyway, back to my point about leaving non-DT support in a driver, the
point is still valid only for drivers, not for platforms/boards. So if
there are no boards supported using board files in mainline that could
benefit from this driver, then this driver can be safely made DT-only,
because no new non-DT platforms/boards can be added.

Best regards,
Tomasz

[Florian Meier]

2013/11/14 Tomasz Figa <tomas...@gmail.com>:

It is very confusing. I agree.
There is already a DMA driver with a proprietary API in the downstream
kernel. The firmware already creates this mask and passes it to this
proprietary driver.
There was already a discussion about this in the first version thread
that (as long as I understand it) resulted in "we should pass this
mask on to the driver via device tree". So I did that. I have no idea
about how this firmware->devicetree interface will take place, but
since I didn't want to run in circles I hardcoded it in the device
tree.

A fridge is still a working fridge, even if no beer is inside ;-)
Ok, bad example, but you will get an error message anyway when you try
to get a channel.

> Anyway, back to my point about leaving non-DT support in a driver, the
> point is still valid only for drivers, not for platforms/boards. So if
> there are no boards supported using board files in mainline that could
> benefit from this driver, then this driver can be safely made DT-only,
> because no new non-DT platforms/boards can be added.

I don't have a telling argument against this, but just thought writing
it this way will
make the migration of the downstream kernel to upstream easier, but if you say I
should change it, I will of course do that.
I am becoming desperate anyway that this migration will ever fully
take place....

Greetings,
Florian

[Tomasz Figa]

OK. So the firmware defines what set and clear bits in the mask mean.
It's fine then.

I'm just presenting you the possible options. You are still free to have
non-DT support in the driver, but if you don't need it (because you can't
have any new non-DT platforms in mainline) then you can simplify some
code.

However the driver shouldn't be left with illusionary support for non-DT
platforms until you decide to implement that. Instead, if you don't want
to add non-DT support now, just make the driver DT-only, while keeping
its design in a way allowing you to add non-DT support in future.

In other words, a driver should not be able to probe using board files
if support for such probing method is not available in it yet.

> I am becoming desperate anyway that this migration will ever fully
> take place....

Why not? It's just a matter of people like you working on this (and
addressing some review comments ;)).

Best regards,
Tomasz

[Florian Meier]

Yes, this mask is actually an "I am not using this channel"-mask.

This statement hits the nail on the head. Thank you!

> In other words, a driver should not be able to probe using board files
> if support for such probing method is not available in it yet.

That is meaningful. So would the following be ok?

+ .....
+ if (pdev->dev.of_node) {
+ .....
+ } else {
+ dev_err(&pdev->dev,
+ "Failed to initialize channels, because device
tree not available: %d\n", rc);

+ bcm2835_dma_free(od);
+ return rc;
+ }
+

+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
+

+ .....

>> I am becoming desperate anyway that this migration will ever fully
>> take place....
>
> Why not? It's just a matter of people like you working on this (and
> addressing some review comments ;)).

The most common comment about this is that people will not put effort in
the upstream kernel as long as there is no comfortable way for debugging
in the upstream kernel (i.e. at least USB support).......

Greetings,
Florian

[Tomasz Figa]

I mean, something closer to:

static int bcm2835_dma_probe(struct platform_device *pdev)
{
uint32_t chan_mask;
// ...

if (pdev->dev.of_node) {
rc = of_property_read_u32(..., &chan_mask);
if (rc) {
// Error out
}
} else {
// Error message
return -EINVAL;
}

// ...
// Channel registration loop (independent of any OF functions)
// ...

if (pdev->dev.of_node) {
rc = of_dma_controller_register(...);
// ...
}

// ...

}

> >> I am becoming desperate anyway that this migration will ever fully
> >> take place....
> >
> > Why not? It's just a matter of people like you working on this (and
> > addressing some review comments ;)).
>
> The most common comment about this is that people will not put effort in
> the upstream kernel as long as there is no comfortable way for debugging
> in the upstream kernel (i.e. at least USB support).......

Right, you need USB to have ethernet working. Still, IMHO UART (for
console) + ethernet (for file transfer or NFS root) is the reasonable
setup allowing you to debug further drivers in a comfortable way.

Best regards,
Tomasz

[Florian Meier]

> I mean, something closer to:

> .....

Ok :-)

>> >> I am becoming desperate anyway that this migration will ever fully
>> >> take place....
>> >
>> > Why not? It's just a matter of people like you working on this (and
>> > addressing some review comments ;)).
>>
>> The most common comment about this is that people will not put effort in
>> the upstream kernel as long as there is no comfortable way for debugging
>> in the upstream kernel (i.e. at least USB support).......
>
> Right, you need USB to have ethernet working. Still, IMHO UART (for
> console) + ethernet (for file transfer or NFS root) is the reasonable
> setup allowing you to debug further drivers in a comfortable way.

I am fine with UART and switching SD cards :-)
But apparently this is not generally accepted.

Greetings,
Florian

[Tomasz Figa]

On Thursday 14 of November 2013 17:14:31 Florian Meier wrote:
> >> >> I am becoming desperate anyway that this migration will ever fully
> >> >> take place....
> >> >
> >> > Why not? It's just a matter of people like you working on this (and
> >> > addressing some review comments ;)).
> >>
> >> The most common comment about this is that people will not put effort in
> >> the upstream kernel as long as there is no comfortable way for debugging
> >> in the upstream kernel (i.e. at least USB support).......
> >
> > Right, you need USB to have ethernet working. Still, IMHO UART (for
> > console) + ethernet (for file transfer or NFS root) is the reasonable
> > setup allowing you to debug further drivers in a comfortable way.
>
> I am fine with UART and switching SD cards :-)
> But apparently this is not generally accepted.

Still, isn't some work on USB support for RPi already going on? I believe
Matt Porter (now on Cc) has been working on unifying dwc2 host-mode
driver with Samsung s3c-hsotg device-mode driver (for the same IP) to
get full OTG support on all applicable platforms.

Best regards,
Tomasz

[Florian Meier]

2013/11/14 Tomasz Figa <tomas...@gmail.com>:

> On Thursday 14 of November 2013 17:14:31 Florian Meier wrote:
>> >> >> I am becoming desperate anyway that this migration will ever fully
>> >> >> take place....
>> >> >
>> >> > Why not? It's just a matter of people like you working on this (and
>> >> > addressing some review comments ;)).
>> >>
>> >> The most common comment about this is that people will not put effort in
>> >> the upstream kernel as long as there is no comfortable way for debugging
>> >> in the upstream kernel (i.e. at least USB support).......
>> >
>> > Right, you need USB to have ethernet working. Still, IMHO UART (for
>> > console) + ethernet (for file transfer or NFS root) is the reasonable
>> > setup allowing you to debug further drivers in a comfortable way.
>>
>> I am fine with UART and switching SD cards :-)
>> But apparently this is not generally accepted.
>
> Still, isn't some work on USB support for RPi already going on? I believe
> Matt Porter (now on Cc) has been working on unifying dwc2 host-mode
> driver with Samsung s3c-hsotg device-mode driver (for the same IP) to
> get full OTG support on all applicable platforms.

That sounds great! I never heard about that.
Maybe some day it really happens that Raspbian uses the upstream kernel :-)

[Matt Porter]

On Thu, Nov 14, 2013 at 05:23:08PM +0100, Tomasz Figa wrote:
> On Thursday 14 of November 2013 17:14:31 Florian Meier wrote:
> > >> >> I am becoming desperate anyway that this migration will ever fully
> > >> >> take place....
> > >> >
> > >> > Why not? It's just a matter of people like you working on this (and
> > >> > addressing some review comments ;)).
> > >>
> > >> The most common comment about this is that people will not put effort in
> > >> the upstream kernel as long as there is no comfortable way for debugging
> > >> in the upstream kernel (i.e. at least USB support).......
> > >
> > > Right, you need USB to have ethernet working. Still, IMHO UART (for
> > > console) + ethernet (for file transfer or NFS root) is the reasonable
> > > setup allowing you to debug further drivers in a comfortable way.
> >
> > I am fine with UART and switching SD cards :-)
> > But apparently this is not generally accepted.
>
> Still, isn't some work on USB support for RPi already going on? I believe
> Matt Porter (now on Cc) has been working on unifying dwc2 host-mode
> driver with Samsung s3c-hsotg device-mode driver (for the same IP) to
> get full OTG support on all applicable platforms.

Baby steps in that direction, yes. I need to finish the basic s3c-hsotg
and dwc2 host only enablement for my platform and then will be focused on
combining them.

-Matt

[Florian Meier]

Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
Currently it only supports cyclic DMA.

Signed-off-by: Florian Meier <floria...@koalo.de>
---

Fifth version with better error handling in probe.

.../devicetree/bindings/dma/bcm2835-dma.txt | 56 ++

drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +

drivers/dma/bcm2835-dma.c | 749 +++++++++++++++++++++
4 files changed, 812 insertions(+)

create mode 100644 Documentation/devicetree/bindings/dma/bcm2835-dma.txt
create mode 100644 drivers/dma/bcm2835-dma.c

diff --git a/Documentation/devicetree/bindings/dma/bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt

new file mode 100644
index 0000000..7d91019
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/bcm2835-dma.txt
@@ -0,0 +1,56 @@

+* BCM2835 DMA controller
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-dma".
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain the DMA interrupts associated
+ to the DMA channels in ascending order.
+ First cell is the IRQ bank.
+ Second cell is the IRQ number.
+- #dma-cells: Must be <1>, used to represent the number of integer cells in
+ the dmas property of client devices.

+- brcm,dma-channel-mask: Bit mask representing the channels

+ not used by the firmware.

+
+Example:
+
+dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16
+ 1 17
+ 1 18
+ 1 19
+ 1 20
+ 1 21
+ 1 22
+ 1 23
+ 1 24
+ 1 25
+ 1 26
+ 1 27
+ 1 28>;

+
+ #dma-cells = <1>;

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
new file mode 100644

index 0000000..bc26398
--- /dev/null
+++ b/drivers/dma/bcm2835-dma.c
@@ -0,0 +1,749 @@

+ int rc = 0;
+

+ return rc;
+}
+

+ return -EINVAL;
+ }
+

+static int bcm2835_dma_probe(struct platform_device *pdev)
+{
+ struct bcm2835_dmadev *od;
+ struct resource *dma_res = NULL;
+ void __iomem *dma_base = NULL;
+ int rc = 0;
+ int i = 0;
+ int irq;
+ uint32_t chans_available;

+ if (pdev->dev.of_node) {

+ /* Request DMA channel mask from device tree */

+ if (of_property_read_u32(pdev->dev.of_node,
+ "brcm,dma-channel-mask",
+ &chans_available)) {

+ dev_err(&pdev->dev, "Failed to get channel mask\n");

+ bcm2835_dma_free(od);
+ return -EINVAL;
+ }

+ } else {
+ dev_err(&pdev->dev, "Failed to get channel mask. No device tree.\n");

+ bcm2835_dma_free(od);
+ return -EINVAL;
+ }
+

+ /* do not use the FIQ and BULK channels */
+ chans_available &= ~0xD;
+
+ for (i = 0; i < pdev->num_resources; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ break;
+
+ if (chans_available & (1 << i)) {
+ rc = bcm2835_dma_chan_init(od, i, irq);
+ if (rc) {

+ bcm2835_dma_free(od);
+ return rc;
+ }
+ }
+ }
+
+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
+

+ if (pdev->dev.of_node) {

+ /* Device-tree DMA controller registration */
+ rc = of_dma_controller_register(pdev->dev.of_node,
+ bcm2835_dma_xlate, od);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed to register DMA controller\n");

+ bcm2835_dma_free(od);
+ return rc;
+ }
+ }
+

+ rc = dma_async_device_register(&od->ddev);
+ if (rc) {

+ dev_err(&pdev->dev,
+ "Failed to register slave DMA engine device: %d\n", rc);

+ bcm2835_dma_free(od);
+ return rc;
+ }
+

+ dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
+

+ return rc;
+}
+

+static int bcm2835_dma_remove(struct platform_device *pdev)
+{
+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
+

+ dma_async_device_unregister(&od->ddev);
+ bcm2835_dma_free(od);
+

+ return 0;
+}
+
+static struct platform_driver bcm2835_dma_driver = {
+ .probe = bcm2835_dma_probe,
+ .remove = bcm2835_dma_remove,
+ .driver = {
+ .name = "bcm2835-dma",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
+ },
+};
+
+module_platform_driver(bcm2835_dma_driver);
+
+MODULE_ALIAS("platform:bcm2835-dma");
+MODULE_DESCRIPTION("BCM2835 DMA engine driver");
+MODULE_AUTHOR("Florian Meier <floria...@koalo.de>");
+MODULE_LICENSE("GPL v2");
--

1.8.1.2

[Joe Perches]

On Fri, 2013-11-15 at 17:28 +0100, Florian Meier wrote:
> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.

trivial style notes:

> diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
[]

> +/* DMA CS Control and Status bits */
> +#define BCM2835_DMA_ACTIVE (1 << 0)
> +#define BCM2835_DMA_INT (1 << 2)
> +#define BCM2835_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
> +#define BCM2835_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
> +#define BCM2835_DMA_ERR (1 << 8)
> +#define BCM2835_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
> +#define BCM2835_DMA_RESET (1 << 31) /* WO, self clearing */

These could use the BIT macro

> +#define BCM2835_DMA_DATA_TYPE_S8 1
> +#define BCM2835_DMA_DATA_TYPE_S16 2
> +#define BCM2835_DMA_DATA_TYPE_S32 4
> +#define BCM2835_DMA_DATA_TYPE_S128 16

Are these sizeof(s8), sizeof(s16), sizeof(s32)?
Is there a S64's? Are there any s128's?

> +static int bcm2835_dma_abort(void __iomem *dma_chan_base)
> +{
> + unsigned long int cs;
> + int rc = 0;

Perhaps better without using an automatic for rc
and using direct returns.

> +
> + cs = readl(dma_chan_base + BCM2835_DMA_CS);
> +
> + if (BCM2835_DMA_ACTIVE & cs) {

if (!(cs & BCM2835_DMA_ACTIVE))
return 0;

and avoid the indent level and use consistent
(cs & bit) style through the routine instead
of mixing (bit & cs) and (cs & bit)

> + long int timeout = 10000;

Move timeout to start of routine.

> + /* write 0 to the active bit - pause the DMA */
> + writel(0, dma_chan_base + BCM2835_DMA_CS);
> +
> + /* wait for any current AXI transfer to complete */
> + while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)
> + cs = readl(dma_chan_base + BCM2835_DMA_CS);
> +
> + if (cs & BCM2835_DMA_ISPAUSED) {
> + /* we'll un-pause when we set of our next DMA */
> + rc = -ETIMEDOUT;

return -ETIMEDOUT;

and avoid another indentation level.

> +
> + } else if (BCM2835_DMA_ACTIVE & cs) {
> + /* terminate the control block chain */
> + writel(0, dma_chan_base + BCM2835_DMA_NEXTCB);
> +
> + /* abort the whole DMA */
> + writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
> + dma_chan_base + BCM2835_DMA_CS);
> + }
> + }
> +
> + return rc;
> +}

So perhaps this becomes:

static int bcm2835_dma_abort(void __iomem *dma_chan_base)
{
unsigned long int cs;
long timeout;

cs = readl(dma_chan_base + BCM2835_DMA_CS);

+ if (!(cs & BCM2835_DMA_ACTIVE))
return 0;

/* write 0 to the active bit - pause the DMA */

writel(0, dma_chan_base + BCM2835_DMA_CS);

/* wait for any current AXI transfer to complete */

timeout = 10000;

while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)

cs = readl(dma_chan_base + BCM2835_DMA_CS);

/* we'll un-pause when we set of our next DMA */

if (cs & BCM2835_DMA_ISPAUSED)
return -ETIMEDOUT;

if (!(cs & BCM2835_DMA_ACTIVE))
return 0;

/* terminate the control block chain */

writel(0, dma_chan_base + BCM2835_DMA_NEXTCB);

/* abort the whole DMA */

writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
dma_chan_base + BCM2835_DMA_CS);

return 0;
}

[]

> +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> +{
> + unsigned i;
> + size_t size;

Please set size to 0 here and not in the for loop

> +
> + for (size = i = 0; i < d->frames; i++) {

[]

> +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
> + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
> + size_t period_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{

> + /* Allocate memory for control blocks */
> + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
> + d->control_block_base = dma_alloc_coherent(chan->device->dev,
> + d->control_block_size, &d->control_block_base_phys,
> + GFP_NOWAIT);
> +
> + if (!d->control_block_base) {
> + kfree(d);
> + dev_err(chan->device->dev,
> + "%s: Memory allocation error\n", __func__);

Please use dma_zalloc_coherent and the OOM message
isn't necessary as dma_alloc_coherent has a generic
OOM message.

> + return NULL;
> + }
> +
> + memset(d->control_block_base, 0, d->control_block_size);

unnecessary with dma_zalloc_coherent

[Florian Meier]

Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
Currently it only supports cyclic DMA.

Signed-off-by: Florian Meier <floria...@koalo.de>
---

Sixth version with some style improvements by Joe.
sizeof(s128) doesn't work. Therefore, still hardcoded byte counts.

.../devicetree/bindings/dma/bcm2835-dma.txt | 56 ++
drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +

drivers/dma/bcm2835-dma.c | 744 +++++++++++++++++++++
4 files changed, 807 insertions(+)

index 0000000..23c7fb6
--- /dev/null
+++ b/drivers/dma/bcm2835-dma.c
@@ -0,0 +1,744 @@

+/* DMA CS Control and Status bits */

+#define BCM2835_DMA_ACTIVE BIT(0)
+#define BCM2835_DMA_INT BIT(2)
+#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
+#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
+#define BCM2835_DMA_ERR BIT(8)
+#define BCM2835_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */
+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
+
+#define BCM2835_DMA_INT_EN BIT(0)
+#define BCM2835_DMA_D_INC BIT(4)
+#define BCM2835_DMA_D_DREQ BIT(6)
+#define BCM2835_DMA_S_INC BIT(8)
+#define BCM2835_DMA_S_DREQ BIT(10)

+
+#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
+

+#define BCM2835_DMA_DATA_TYPE_S8 1
+#define BCM2835_DMA_DATA_TYPE_S16 2
+#define BCM2835_DMA_DATA_TYPE_S32 4
+#define BCM2835_DMA_DATA_TYPE_S128 16

+static int bcm2835_dma_abort(void __iomem *dma_chan_base)
+{
+ unsigned long int cs;

+ long int timeout = 10000;

+
+ cs = readl(dma_chan_base + BCM2835_DMA_CS);

+ if (!(cs & BCM2835_DMA_ACTIVE))
+ return 0;
+

+ /* write 0 to the active bit - pause the DMA */
+ writel(0, dma_chan_base + BCM2835_DMA_CS);
+
+ /* wait for any current AXI transfer to complete */
+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)
+ cs = readl(dma_chan_base + BCM2835_DMA_CS);
+

+ /* we'll un-pause when we set of our next DMA */
+ if (cs & BCM2835_DMA_ISPAUSED)

+ return -ETIMEDOUT;
+

+ if (!(cs & BCM2835_DMA_ACTIVE))

+ return 0;
+

+ /* terminate the control block chain */
+ writel(0, dma_chan_base + BCM2835_DMA_NEXTCB);
+
+ /* abort the whole DMA */
+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
+ dma_chan_base + BCM2835_DMA_CS);
+

+ return 0;
+}
+

+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
+ struct bcm2835_desc *d;
+
+ if (!vd) {
+ c->desc = NULL;
+ return;
+ }
+
+ list_del(&vd->node);
+
+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
+
+ dsb(); /* ARM data synchronization (push) operation */
+
+ writel(d->control_block_base_phys, c->dma_chan_base + BCM2835_DMA_ADDR);

+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+}
+

+static irqreturn_t bcm2835_dma_callback(int irq, void *data)
+{
+ struct bcm2835_chan *c = data;
+ struct bcm2835_desc *d;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+
+ /* acknowledge interrupt */

+ writel(BCM2835_DMA_INT, c->dma_chan_base + BCM2835_DMA_CS);
+

+ d = c->desc;
+
+ if (d) {
+ /* TODO Only works for cyclic DMA */
+ vchan_cyclic_callback(&d->vd);
+ }
+
+ /* keep the DMA engine running */
+ dsb(); /* ARM synchronization barrier */

+ writel(BCM2835_DMA_ACTIVE, c->dma_chan_base + BCM2835_DMA_CS);
+

+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
+{
+ unsigned i;

+ size_t size = 0;
+
+ for (i = 0; i < d->frames; i++) {

+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ enum dma_slave_buswidth dev_width;
+ struct bcm2835_desc *d;
+ dma_addr_t dev_addr;
+ unsigned es, sync_type;
+ unsigned frame;
+
+ /* Grab configuration */
+ if (direction == DMA_DEV_TO_MEM) {
+ dev_addr = c->cfg.src_addr;
+ dev_width = c->cfg.src_addr_width;
+ sync_type = BCM2835_DMA_S_DREQ;
+ } else if (direction == DMA_MEM_TO_DEV) {
+ dev_addr = c->cfg.dst_addr;
+ dev_width = c->cfg.dst_addr_width;
+ sync_type = BCM2835_DMA_D_DREQ;
+ } else {
+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);

+ return NULL;
+ }
+

+ /* Bus width translates to the element size (ES) */
+ switch (dev_width) {
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ es = BCM2835_DMA_DATA_TYPE_S32;
+ break;
+ default:

+ return NULL;
+ }
+

+ /* Now allocate and setup the descriptor. */
+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
+ if (!d)

+ return NULL;
+

+ d->dir = direction;
+ d->frames = buf_len / period_len;

+
+ /* Allocate memory for control blocks */
+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);

+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,

+ d->control_block_size, &d->control_block_base_phys,
+ GFP_NOWAIT);
+
+ if (!d->control_block_base) {
+ kfree(d);

+ return NULL;
+ }
+

+ return NULL;
+

+ int rc = 0;

+
+ return rc;
+}

[Shevchenko, Andriy]

On Fri, 2013-11-15 at 17:28 +0100, Florian Meier wrote:

> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.

Few comments below.

> +++ b/drivers/dma/bcm2835-dma.c
> @@ -0,0 +1,749 @@
> +/*
> + * BCM2835 DMA engine support
> + *
> + * This driver only supports cyclic DMA transfers
> + * as needed for the I2S module.
> + *
> + * Author: Florian Meier, <floria...@koalo.de>

Comma there a bit inconvenient. It would be easier to copy'n'paste
address w/o it.

Up to you.

> + * Copyright 2013
> + *
> + * based on

Maybe 'Based on'?

[]

> +struct bcm2835_chan {

> + int dma_ch;

Do you really need this dma_ prefix?

> + void __iomem *dma_chan_base;
> + int dma_irq_number;

Ditto.

> +#define BCM2835_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
> +#define BCM2835_DMA_RESET (1 << 31) /* WO, self clearing */

You have different style of comments in the file: some of them starts
from capital letter, some not. It would be better to have one style.

> +#define BCM2835_DMA_DATA_TYPE_S8 1
> +#define BCM2835_DMA_DATA_TYPE_S16 2
> +#define BCM2835_DMA_DATA_TYPE_S32 4
> +#define BCM2835_DMA_DATA_TYPE_S128 16

Indentation?

> +#define BCM2835_DMA_CHANIO(dma_base, n) ((dma_base) + BCM2835_DMA_CHAN(n))

dma_base -> base ?

[]

> +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> +{
> + unsigned i;
> + size_t size;

size = 0 here is better.

> + for (size = i = 0; i < d->frames; i++) {
> + struct bcm2835_dma_cb *control_block =
> + &d->control_block_base[i];
> + size_t this_size = control_block->length;
> + dma_addr_t dma;
> +
> + if (d->dir == DMA_DEV_TO_MEM)
> + dma = control_block->dst;
> + else
> + dma = control_block->src;

Do you think it must be dependent on the direction?

Do you have information of how many bytes transferred already in the DMA
controller registers? Would it be better to use it?

> + if (size)
> + size += this_size;
> + else if (addr >= dma && addr < dma + this_size)
> + size += dma + this_size - addr;

+= -> =


[]

> +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
> + dma_cookie_t cookie, struct dma_tx_state *txstate)
> +{

> + } else {
> + txstate->residue = 0;

Not needed since it's default by dmaengine.

> +static void bcm2835_dma_issue_pending(struct dma_chan *chan)
> +{

> +}

> +
> +

Redundant empty line

> +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(

> + /* The following fields are not used here */
> + control_block->stride = 0;
> + control_block->pad[0] = 0;
> + control_block->pad[1] = 0;

You have already them zeroed by memset.

[]

> +static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
> + struct dma_slave_config *cfg)
> +{

> + (cfg->direction != DMA_DEV_TO_MEM &&
> + cfg->direction != DMA_MEM_TO_DEV)) {

We have a helper for those two above.

[]

> +static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
> +{
> + struct bcm2835_chan *c;
> +
> + c = kzalloc(sizeof(*c), GFP_KERNEL);

Why this can't be devm_kzalloc?

[]

> +static int bcm2835_dma_probe(struct platform_device *pdev)
> +{

> + struct resource *dma_res = NULL;
> + void __iomem *dma_base = NULL;
> + int rc = 0;
> + int i = 0;

Useless assignments.

[]

> + if (!pdev->dev.dma_mask)
> + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
> +
> + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
> + if (rc)
> + return rc;
> + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));

There is nice helper you may use instead of those two above and remove
'if' condition as well.

[]

> +}

[]

> +module_platform_driver(bcm2835_dma_driver);

Is it possible to get driver initialized after that one that uses it?

--
Andy Shevchenko <andriy.s...@intel.com>
Intel Finland Oy
---------------------------------------------------------------------
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[Russell King - ARM Linux]

On Fri, Nov 15, 2013 at 09:03:36AM -0800, Joe Perches wrote:
> On Fri, 2013-11-15 at 17:28 +0100, Florian Meier wrote:
> > +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> > +{
> > + unsigned i;
> > + size_t size;
>
> Please set size to 0 here and not in the for loop
> > +
> > + for (size = i = 0; i < d->frames; i++) {

I disagree with that comment; I think the above is not only cleaner, but
also more obvious that _this_ loop is calculating _this_ size.

[Russell King - ARM Linux]

On Fri, Nov 15, 2013 at 05:43:45PM +0000, Shevchenko, Andriy wrote:
> On Fri, 2013-11-15 at 17:28 +0100, Florian Meier wrote:
> > +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> > +{
> > + unsigned i;
> > + size_t size;
>
> size = 0 here is better.

See my other comment to Joe.

> > + for (size = i = 0; i < d->frames; i++) {
> > + struct bcm2835_dma_cb *control_block =
> > + &d->control_block_base[i];
> > + size_t this_size = control_block->length;
> > + dma_addr_t dma;
> > +
> > + if (d->dir == DMA_DEV_TO_MEM)
> > + dma = control_block->dst;
> > + else
> > + dma = control_block->src;
>
> Do you think it must be dependent on the direction?

Of course it does. Take a moment to think about it please.

> Do you have information of how many bytes transferred already in the DMA
> controller registers? Would it be better to use it?
>
> > + if (size)
> > + size += this_size;
> > + else if (addr >= dma && addr < dma + this_size)
> > + size += dma + this_size - addr;
>
> += -> =

No functional change, as 'size' has to be initialised anyway. The
code is fine.

> > + if (!pdev->dev.dma_mask)
> > + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
> > +
> > + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
> > + if (rc)
> > + return rc;
> > + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
>
> There is nice helper you may use instead of those two above and remove
> 'if' condition as well.

There is _now_ but at the time this is being developed, it wasn't there.
Such a change is probably only appropriate at least after -rc1 has
happened. Since I'm the one who introduced that helper, and I haven't
said to use it yet in this driver, that suggests I've already thought
about this point...

> > +module_platform_driver(bcm2835_dma_driver);
>
> Is it possible to get driver initialized after that one that uses it?

Doesn't quite make sense. If you're asking whether other drivers can
try to make use of this driver before it's initialised, then the answer
is no. We have mechanisms to cope with that - see deferred probing.

[Joe Perches]

On Fri, 2013-11-15 at 17:43 +0000, Russell King - ARM Linux wrote:
> On Fri, Nov 15, 2013 at 09:03:36AM -0800, Joe Perches wrote:
> > On Fri, 2013-11-15 at 17:28 +0100, Florian Meier wrote:
> > > +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> > > +{
> > > + unsigned i;
> > > + size_t size;
> >
> > Please set size to 0 here and not in the for loop
> > > +
> > > + for (size = i = 0; i < d->frames; i++) {
>
> I disagree with that comment; I think the above is not only cleaner, but
> also more obvious that _this_ loop is calculating _this_ size.

I think that using
size_t size = 0;
is not only _much_ more commonly used
throughout the kernel but makes it
clearer that the initialization of the
return value is done before the loop.

Reasonable minds can differ and there
is no style guide that prefers one over
the other.

No matter really to me.
As I said, it's trivial.

cheers, Joe

[Andy Shevchenko]

> On Fri, Nov 15, 2013 at 7:51 PM, Russell King - ARM Linux <li...@arm.linux.org.uk> wrote:
>>
>> On Fri, Nov 15, 2013 at 05:43:45PM +0000, Shevchenko, Andriy wrote:
>>
>> > > +module_platform_driver(bcm2835_dma_driver);
>> >
>> > Is it possible to get driver initialized after that one that uses it?
>>
>> Doesn't quite make sense. If you're asking whether other drivers can
>> try to make use of this driver before it's initialised, then the answer
>> is no. We have mechanisms to cope with that - see deferred probing.

The reason why I was asking about I'm just wondering what we have to
do with existing drivers. Shall we convert them to be initialized as
normal platform drivers instead of subsys_initcall?

--
With Best Regards,
Andy Shevchenko

[Mark Brown]

On Sat, Nov 16, 2013 at 11:37:54AM +0200, Andy Shevchenko wrote:

> The reason why I was asking about I'm just wondering what we have to do
> with existing drivers. Shall we convert them to be initialized as normal
> platform drivers instead of subsys_initcall?

We should in general be moving in that direction however it does need a
bit of care to make sure that there aren't any dependencies which do
things like discard error codes, fail to check errors or treat errors as
hard failures.

[Russell King - ARM Linux]

I don't agree: on platforms which have done this, it's very difficult to
tell from reading the kernel message log whether things came up correctly
because there's soo much spew from deferred probing it's virtually
impossible to tell whether component X initialised or whether that error
about resource Y missing was ever resolved.

The only way that can be checked is when things work (or don't) from
userspace.

It's soo bad on some platforms that reading the kernel boot log is a
total waste of time; you don't get any useful information from it.

If we want kernel boot logs to be useful, we really need to shut up *all*
the drivers and subsystems whinging about being deferred probing, and only
have the driver model core reporting this status - maybe only allow
output about why at debug level or similar.

[Mark Brown]

On Sat, Nov 16, 2013 at 11:41:34AM +0000, Russell King - ARM Linux wrote:
> On Sat, Nov 16, 2013 at 11:27:54AM +0000, Mark Brown wrote:

> > We should in general be moving in that direction however it does need a
> > bit of care to make sure that there aren't any dependencies which do
> > things like discard error codes, fail to check errors or treat errors as
> > hard failures.

> I don't agree: on platforms which have done this, it's very difficult to
> tell from reading the kernel message log whether things came up correctly
> because there's soo much spew from deferred probing it's virtually
> impossible to tell whether component X initialised or whether that error
> about resource Y missing was ever resolved.

I do agree that deferred programming is far too chatty - there's a
usability issue there. This bites me a lot on some of my systems too, I
tend to read my logs with grep a lot which isn't awesome.

> If we want kernel boot logs to be useful, we really need to shut up *all*
> the drivers and subsystems whinging about being deferred probing, and only
> have the driver model core reporting this status - maybe only allow
> output about why at debug level or similar.

Yes, some sort of standardisation of how this stuff gets reported would
give us much better control of these things.

[Florian Meier]

Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
Currently it only supports cyclic DMA.

Signed-off-by: Florian Meier <floria...@koalo.de>
---

This version includes some more style improvements
suggested in the previous thread.

.../devicetree/bindings/dma/bcm2835-dma.txt | 56 ++
drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +

drivers/dma/bcm2835-dma.c | 736 ++++++++++++++++++++
4 files changed, 799 insertions(+)

index 0000000..4b4c673
--- /dev/null
+++ b/drivers/dma/bcm2835-dma.c
@@ -0,0 +1,736 @@

+/*
+ * BCM2835 DMA engine support
+ *
+ * This driver only supports cyclic DMA transfers
+ * as needed for the I2S module.
+ *

+ * Author: Florian Meier <floria...@koalo.de>

+ * Copyright 2013
+ *

+ * Based on

+ * OMAP DMAengine support by Russell King
+ *
+ * BCM2708 DMA Driver
+ * Copyright (C) 2010 Broadcom
+ *
+ * Raspberry Pi PCM I2S ALSA Driver

+ * Copyright (c) by Phil Poole 2013
+ *

+ * MARVELL MMP Peripheral DMA Driver
+ * Copyright 2012 Marvell International Ltd.

+ *

+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+
+#include "virt-dma.h"
+
+struct bcm2835_dmadev {
+ struct dma_device ddev;
+ spinlock_t lock;

+ void __iomem *base;

+ struct device_dma_parameters dma_parms;
+};
+
+struct bcm2835_dma_cb {
+ uint32_t info;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t length;
+ uint32_t stride;
+ uint32_t next;
+ uint32_t pad[2];
+};
+
+struct bcm2835_chan {
+ struct virt_dma_chan vc;
+ struct list_head node;
+
+ struct dma_slave_config cfg;
+ bool cyclic;
+ unsigned dreq;
+

+ int ch;

+ struct bcm2835_desc *desc;
+

+ void __iomem *chan_base;
+ int irq_number;

+#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */

+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
+
+#define BCM2835_DMA_INT_EN BIT(0)
+#define BCM2835_DMA_D_INC BIT(4)
+#define BCM2835_DMA_D_DREQ BIT(6)
+#define BCM2835_DMA_S_INC BIT(8)
+#define BCM2835_DMA_S_DREQ BIT(10)
+
+#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
+

+#define BCM2835_DMA_DATA_TYPE_S8 1
+#define BCM2835_DMA_DATA_TYPE_S16 2
+#define BCM2835_DMA_DATA_TYPE_S32 4
+#define BCM2835_DMA_DATA_TYPE_S128 16

+
+/* Valid only for channels 0 - 14, 15 has its own base address */
+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
+#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))

+static int bcm2835_dma_abort(void __iomem *chan_base)

+{
+ unsigned long int cs;
+ long int timeout = 10000;
+

+ cs = readl(chan_base + BCM2835_DMA_CS);

+ if (!(cs & BCM2835_DMA_ACTIVE))
+ return 0;
+

+ /* Write 0 to the active bit - Pause the DMA */
+ writel(0, chan_base + BCM2835_DMA_CS);
+
+ /* Wait for any current AXI transfer to complete */

+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)

+ cs = readl(chan_base + BCM2835_DMA_CS);
+
+ /* We'll un-pause when we set of our next DMA */

+ if (cs & BCM2835_DMA_ISPAUSED)
+ return -ETIMEDOUT;
+
+ if (!(cs & BCM2835_DMA_ACTIVE))
+ return 0;
+

+ /* Terminate the control block chain */
+ writel(0, chan_base + BCM2835_DMA_NEXTCB);
+
+ /* Abort the whole DMA */
+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
+ chan_base + BCM2835_DMA_CS);

+
+ return 0;
+}
+
+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
+ struct bcm2835_desc *d;
+
+ if (!vd) {
+ c->desc = NULL;
+ return;
+ }
+
+ list_del(&vd->node);
+
+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
+
+ dsb(); /* ARM data synchronization (push) operation */
+

+ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);

+}
+
+static irqreturn_t bcm2835_dma_callback(int irq, void *data)

+{

+ struct bcm2835_chan *c = data;
+ struct bcm2835_desc *d;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+

+ /* Acknowledge interrupt */
+ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);

+
+ d = c->desc;
+
+ if (d) {
+ /* TODO Only works for cyclic DMA */
+ vchan_cyclic_callback(&d->vd);
+ }
+

+ /* Keep the DMA engine running */

+ dsb(); /* ARM synchronization barrier */

+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);

+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)

+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+
+ dev_dbg(c->vc.chan.device->dev,

+ "Allocating DMA channel %i\n", c->ch);
+
+ return request_irq(c->irq_number,

+ bcm2835_dma_callback, 0, "DMA IRQ", c);
+}
+
+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)

+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+
+ vchan_free_chan_resources(&c->vc);

+ free_irq(c->irq_number, c);
+
+ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);

+}
+
+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
+{
+ return d->size;
+}
+

+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
+{
+ unsigned i;
+ size_t size;

+
+ for (size = i = 0; i < d->frames; i++) {

+ struct bcm2835_dma_cb *control_block =
+ &d->control_block_base[i];
+ size_t this_size = control_block->length;
+ dma_addr_t dma;
+
+ if (d->dir == DMA_DEV_TO_MEM)
+ dma = control_block->dst;
+ else
+ dma = control_block->src;

+

+ if (size)
+ size += this_size;
+ else if (addr >= dma && addr < dma + this_size)
+ size += dma + this_size - addr;

+ }
+
+ return size;
+}
+

+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ struct virt_dma_desc *vd;
+ enum dma_status ret;
+ unsigned long flags;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_SUCCESS || !txstate)
+ return ret;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ vd = vchan_find_desc(&c->vc, cookie);
+ if (vd) {
+ txstate->residue =
+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
+ struct bcm2835_desc *d = c->desc;
+ dma_addr_t pos;

+
+ if (d->dir == DMA_MEM_TO_DEV)

+ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
+ else if (d->dir == DMA_DEV_TO_MEM)
+ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);

+ else
+ pos = 0;
+
+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);

+ } else {
+ txstate->residue = 0;

+ }
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return ret;
+}
+

+static void bcm2835_dma_issue_pending(struct dma_chan *chan)
+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ unsigned long flags;
+

+ c->cyclic = true; /* Nothing else is implemented */

+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (vchan_issue_pending(&c->vc) && !c->desc)
+ bcm2835_dma_start_desc(c);
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+}
+

+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(

+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)

+{

+ struct bcm2835_dma_cb *control_block =

+ &d->control_block_base[frame];
+
+ /* Setup adresses */

+ if (d->dir == DMA_DEV_TO_MEM) {

+ return vchan_tx_prep(&c->vc, &d->vd, flags);
+}
+

+static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
+ struct dma_slave_config *cfg)
+{

+ if ((cfg->direction == DMA_DEV_TO_MEM &&
+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (cfg->direction == DMA_MEM_TO_DEV &&
+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||

+ !is_slave_direction(cfg->direction)) {

+ bcm2835_dma_abort(c->chan_base);

+
+ /* Wait for stopping */
+ while (timeout > 0) {
+ timeout--;

+ if (!(readl(c->chan_base + BCM2835_DMA_CS) &

+ BCM2835_DMA_ACTIVE))
+ break;
+
+ cpu_relax();
+ }
+
+ if (timeout <= 0)
+ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
+ }
+
+ vchan_get_all_descriptors(&c->vc, &head);
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+ vchan_dma_desc_free_list(&c->vc, &head);
+
+ return 0;
+}
+
+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ unsigned long arg)

+{

+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+ int ret;
+
+ switch (cmd) {
+ case DMA_SLAVE_CONFIG:
+ return bcm2835_dma_slave_config(c,
+ (struct dma_slave_config *)arg);
+
+ case DMA_TERMINATE_ALL:
+ bcm2835_dma_terminate_all(c);
+ break;
+
+ default:
+ ret = -ENXIO;
+ break;
+ }
+
+ return ret;
+}
+

+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
+{
+ struct bcm2835_chan *c;
+

+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);

+ if (!c)
+ return -ENOMEM;
+
+ c->vc.desc_free = bcm2835_dma_desc_free;
+ vchan_init(&c->vc, &d->ddev);
+ INIT_LIST_HEAD(&c->node);
+
+ d->ddev.chancnt++;
+

+ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
+ c->ch = chan_id;
+ c->irq_number = irq;

+
+ return 0;
+}
+
+static void bcm2835_dma_free(struct bcm2835_dmadev *od)
+{
+ while (!list_empty(&od->ddev.channels)) {
+ struct bcm2835_chan *c = list_first_entry(&od->ddev.channels,
+ struct bcm2835_chan, vc.chan.device_node);
+
+ list_del(&c->vc.chan.device_node);
+ tasklet_kill(&c->vc.task);
+ }

+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id bcm2835_dma_of_match[] = {
+ { .compatible = "brcm,bcm2835-dma", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
+#endif
+

+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,

+ struct of_dma *ofdma)
+{
+ struct bcm2835_dmadev *d = ofdma->of_dma_data;
+ struct dma_chan *chan, *candidate;
+
+retry:
+ candidate = NULL;
+

+ /* Walk the list of channels registered with the current instance and

+ * find one that is currently unused */
+ list_for_each_entry(chan, &d->ddev.channels, device_node)
+ if (chan->client_count == 0) {
+ candidate = chan;
+ break;
+ }
+
+ if (!candidate)
+ return NULL;
+
+ /* dma_get_slave_channel will return NULL if we lost a race between
+ * the lookup and the reservation */
+ chan = dma_get_slave_channel(candidate);
+
+ if (chan) {
+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
+
+ /* Set DREQ from param */

+ c->dreq = spec->args[0];

+
+ return chan;
+ }
+
+ goto retry;
+}
+
+static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
+ struct dma_slave_caps *caps)
+{
+ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ caps->cmd_pause = false;
+ caps->cmd_terminate = true;
+
+ return 0;
+}
+

+static int bcm2835_dma_probe(struct platform_device *pdev)
+{

+ struct bcm2835_dmadev *od;
+ struct resource *res;
+ void __iomem *base;
+ int rc;
+ int i;

+ int irq;
+ uint32_t chans_available;
+

+ if (!pdev->dev.dma_mask)
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (rc)
+ return rc;
+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));

+
+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
+ if (!od)
+ return -ENOMEM;
+
+ pdev->dev.dma_parms = &od->dma_parms;
+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
+

+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ od->base = base;

+ /* Do not use the FIQ and BULK channels */

+static int bcm2835_dma_remove(struct platform_device *pdev)
+{

1.7.9.5

[Joe Perches]

On Sun, 2013-11-17 at 16:39 +0100, Florian Meier wrote:
> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.

[]
> diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
[]

> +static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> + unsigned long arg)
> +{
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> + int ret;
> +
> + switch (cmd) {
> + case DMA_SLAVE_CONFIG:
> + return bcm2835_dma_slave_config(c,
> + (struct dma_slave_config *)arg);
> +
> + case DMA_TERMINATE_ALL:
> + bcm2835_dma_terminate_all(c);
> + break;
> +
> + default:
> + ret = -ENXIO;
> + break;
> + }
> +
> + return ret;
> +}

case DMA_TERMINATE_ALL returns an uninitialized ret;

[]

> +static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
> + struct of_dma *ofdma)
> +{
> + struct bcm2835_dmadev *d = ofdma->of_dma_data;
> + struct dma_chan *chan, *candidate;
> +
> +retry:
> + candidate = NULL;
> +
> + /* Walk the list of channels registered with the current instance and
> + * find one that is currently unused */
> + list_for_each_entry(chan, &d->ddev.channels, device_node)
> + if (chan->client_count == 0) {
> + candidate = chan;
> + break;
> + }
> +
> + if (!candidate)
> + return NULL;
> +
> + /* dma_get_slave_channel will return NULL if we lost a race between
> + * the lookup and the reservation */
> + chan = dma_get_slave_channel(candidate);

Can that race happen consistently?
Does this avoid being a tight loop?

> + if (chan) {
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> +
> + /* Set DREQ from param */
> + c->dreq = spec->args[0];
> +
> + return chan;
> + }
> +
> + goto retry;
> +}

Also, I think this would be better as:

if (!chan)
goto retry;

to_bcm2835_dma_chan(chan)->dreq = spec->args[0];

return chan;

[Florian Meier]

Oh yes - stupid mistake. Thank you!

I would say this can not happen.
If I get everything right, the conflicting process will not
get NULL (because it has won the race). In the worst case,
a new process enters the race, but this will only continue until all
channels are used. In that case no candidate exists and the loop will
exit.

At least, the code is directly taken from mmp_pdma.c ;-)

Greetings,
Florian

[Joe Perches]

Neaten code used as a template for other drivers.
Make the code more consistent with kernel styles.

o Convert #defines with (1<<foo) to BIT(foo)
o Alignment wrapping
o Logic inversions to put return at end of functions
o Convert devm_kzalloc with multiply to devm_kcalloc
o typo of Peripheral fix

Signed-off-by: Joe Perches <j...@perches.com>
---

> At least, the code is directly taken from mmp_pdma.c ;-)

Well, maybe the template code should be updated if there
are going to be more of these.

Uncompiled/untested.

drivers/dma/mmp_pdma.c | 204 +++++++++++++++++++++++++------------------------
1 file changed, 105 insertions(+), 99 deletions(-)

diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index dcb1e05..c2658f6 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -5,6 +5,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
@@ -32,38 +33,37 @@
#define DTADR 0x0208
#define DCMD 0x020c

-#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
-#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
-#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
-#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
-#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
-#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
-#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
-#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
-
-#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
-#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
-#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
-#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
-#define DCSR_EORINTR (1 << 9) /* The end of Receive */
-
-#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + \
- (((n) & 0x3f) << 2))
-#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
-#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
+#define DCSR_RUN BIT(31) /* Run Bit (read / write) */
+#define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
+#define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
+#define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
+#define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
+#define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
+#define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
+#define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
+#define DCSR_EORINTR BIT(9) /* The end of Receive */
+
+#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2))
+#define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
+#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */

#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
-#define DDADR_STOP (1 << 0) /* Stop (read / write) */
-
-#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
-#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
-#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
-#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
-#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
+#define DDADR_STOP BIT(0) /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
+#define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
+#define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
+#define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
@@ -132,10 +132,14 @@ struct mmp_pdma_device {
spinlock_t phy_lock; /* protect alloc/free phy channels */
};

-#define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)
-#define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)
-#define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)
-#define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)
+#define tx_to_mmp_pdma_desc(tx) \
+ container_of(tx, struct mmp_pdma_desc_sw, async_tx)
+#define to_mmp_pdma_desc(lh) \
+ container_of(lh, struct mmp_pdma_desc_sw, node)
+#define to_mmp_pdma_chan(dchan) \
+ container_of(dchan, struct mmp_pdma_chan, chan)
+#define to_mmp_pdma_dev(dmadev) \
+ container_of(dmadev, struct mmp_pdma_device, device)

static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
{
@@ -162,19 +166,18 @@ static void enable_chan(struct mmp_pdma_phy *phy)
writel(dalgn, phy->base + DALGN);

reg = (phy->idx << 2) + DCSR;
- writel(readl(phy->base + reg) | DCSR_RUN,
- phy->base + reg);
+ writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg);
}

static void disable_chan(struct mmp_pdma_phy *phy)
{
u32 reg;

- if (phy) {
- reg = (phy->idx << 2) + DCSR;
- writel(readl(phy->base + reg) & ~DCSR_RUN,
- phy->base + reg);
- }
+ if (!phy)
+ return;
+
+ reg = (phy->idx << 2) + DCSR;
+ writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg);
}

static int clear_chan_irq(struct mmp_pdma_phy *phy)
@@ -183,26 +186,27 @@ static int clear_chan_irq(struct mmp_pdma_phy *phy)
u32 dint = readl(phy->base + DINT);
u32 reg = (phy->idx << 2) + DCSR;

- if (dint & BIT(phy->idx)) {
- /* clear irq */
- dcsr = readl(phy->base + reg);
- writel(dcsr, phy->base + reg);
- if ((dcsr & DCSR_BUSERR) && (phy->vchan))
- dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
- return 0;
- }
- return -EAGAIN;
+ if (!(dint & BIT(phy->idx)))
+ return -EAGAIN;
+
+ /* clear irq */
+ dcsr = readl(phy->base + reg);
+ writel(dcsr, phy->base + reg);
+ if ((dcsr & DCSR_BUSERR) && (phy->vchan))
+ dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
+
+ return 0;
}

static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
{
struct mmp_pdma_phy *phy = dev_id;

- if (clear_chan_irq(phy) == 0) {
- tasklet_schedule(&phy->vchan->tasklet);
- return IRQ_HANDLED;
- } else
+ if (clear_chan_irq(phy) != 0)
return IRQ_NONE;
+
+ tasklet_schedule(&phy->vchan->tasklet);
+ return IRQ_HANDLED;
}

static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
@@ -224,8 +228,8 @@ static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)

if (irq_num)
return IRQ_HANDLED;
- else
- return IRQ_NONE;
+
+ return IRQ_NONE;
}

/* lookup free phy channel as descending priority */
@@ -245,9 +249,9 @@ static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
*/

spin_lock_irqsave(&pdev->phy_lock, flags);
- for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) {
+ for (prio = 0; prio <= ((pdev->dma_channels - 1) & 0xf) >> 2; prio++) {
for (i = 0; i < pdev->dma_channels; i++) {
- if (prio != ((i & 0xf) >> 2))
+ if (prio != (i & 0xf) >> 2)
continue;
phy = &pdev->phy[i];
if (!phy->vchan) {
@@ -389,14 +393,16 @@ static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
if (chan->desc_pool)
return 1;

- chan->desc_pool =
- dma_pool_create(dev_name(&dchan->dev->device), chan->dev,
- sizeof(struct mmp_pdma_desc_sw),
- __alignof__(struct mmp_pdma_desc_sw), 0);
+ chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device),
+ chan->dev,
+ sizeof(struct mmp_pdma_desc_sw),
+ __alignof__(struct mmp_pdma_desc_sw),
+ 0);
if (!chan->desc_pool) {
dev_err(chan->dev, "unable to allocate descriptor pool\n");
return -ENOMEM;
}
+
mmp_pdma_free_phy(chan);
chan->idle = true;
chan->dev_addr = 0;
@@ -404,7 +410,7 @@ static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
}

static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
- struct list_head *list)
+ struct list_head *list)
{
struct mmp_pdma_desc_sw *desc, *_desc;

@@ -434,8 +440,8 @@ static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)

static struct dma_async_tx_descriptor *
mmp_pdma_prep_memcpy(struct dma_chan *dchan,
- dma_addr_t dma_dst, dma_addr_t dma_src,
- size_t len, unsigned long flags)
+ dma_addr_t dma_dst, dma_addr_t dma_src,
+ size_t len, unsigned long flags)
{
struct mmp_pdma_chan *chan;
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
@@ -515,8 +521,8 @@ fail:

static struct dma_async_tx_descriptor *
mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
- unsigned int sg_len, enum dma_transfer_direction dir,
- unsigned long flags, void *context)
+ unsigned int sg_len, enum dma_transfer_direction dir,

+ unsigned long flags, void *context)

{
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
@@ -591,10 +597,11 @@ fail:
return NULL;
}

-static struct dma_async_tx_descriptor *mmp_pdma_prep_dma_cyclic(
- struct dma_chan *dchan, dma_addr_t buf_addr, size_t len,
- size_t period_len, enum dma_transfer_direction direction,
- unsigned long flags, void *context)
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
+ dma_addr_t buf_addr, size_t len, size_t period_len,
+ enum dma_transfer_direction direction,

+ unsigned long flags, void *context)

{
struct mmp_pdma_chan *chan;
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
@@ -636,8 +643,8 @@ static struct dma_async_tx_descriptor *mmp_pdma_prep_dma_cyclic(
goto fail;
}

- new->desc.dcmd = chan->dcmd | DCMD_ENDIRQEN |
- (DCMD_LENGTH & period_len);
+ new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN |
+ (DCMD_LENGTH & period_len));
new->desc.dsadr = dma_src;
new->desc.dtadr = dma_dst;

@@ -677,12 +684,11 @@ fail:
}

static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
- unsigned long arg)
+ unsigned long arg)
{
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
struct dma_slave_config *cfg = (void *)arg;
unsigned long flags;
- int ret = 0;
u32 maxburst = 0, addr = 0;
enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;

@@ -739,11 +745,12 @@ static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
return -ENOSYS;
}

- return ret;
+ return 0;
}

static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
- dma_cookie_t cookie, struct dma_tx_state *txstate)
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
{
return dma_cookie_status(dchan, cookie, txstate);
}
@@ -845,15 +852,14 @@ static int mmp_pdma_remove(struct platform_device *op)
return 0;
}

-static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
- int idx, int irq)
+static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq)
{
struct mmp_pdma_phy *phy = &pdev->phy[idx];
struct mmp_pdma_chan *chan;
int ret;

- chan = devm_kzalloc(pdev->dev,
- sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+ chan = devm_kzalloc(pdev->dev, sizeof(struct mmp_pdma_chan),
+ GFP_KERNEL);
if (chan == NULL)
return -ENOMEM;

@@ -861,8 +867,8 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
phy->base = pdev->base;

if (irq) {
- ret = devm_request_irq(pdev->dev, irq,
- mmp_pdma_chan_handler, 0, "pdma", phy);
+ ret = devm_request_irq(pdev->dev, irq, mmp_pdma_chan_handler, 0,
+ "pdma", phy);
if (ret) {
dev_err(pdev->dev, "channel request irq fail!\n");
return ret;
@@ -877,8 +883,7 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
INIT_LIST_HEAD(&chan->chain_running);

/* register virt channel to dma engine */
- list_add_tail(&chan->chan.device_node,
- &pdev->device.channels);
+ list_add_tail(&chan->chan.device_node, &pdev->device.channels);

return 0;
}
@@ -913,13 +918,12 @@ retry:

* the lookup and the reservation */

chan = dma_get_slave_channel(candidate);

- if (chan) {
- struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan);
- c->drcmr = dma_spec->args[0];
- return chan;
- }
+ if (!chan)
+ goto retry;

- goto retry;
+ to_mmp_pdma_chan(chan)->drcmr = dma_spec->args[0];
+
+ return chan;
}

static int mmp_pdma_probe(struct platform_device *op)
@@ -934,6 +938,7 @@ static int mmp_pdma_probe(struct platform_device *op)
pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
if (!pdev)
return -ENOMEM;
+
pdev->dev = &op->dev;

spin_lock_init(&pdev->phy_lock);
@@ -945,8 +950,8 @@ static int mmp_pdma_probe(struct platform_device *op)

of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
if (of_id)
- of_property_read_u32(pdev->dev->of_node,
- "#dma-channels", &dma_channels);
+ of_property_read_u32(pdev->dev->of_node, "#dma-channels",
+ &dma_channels);
else if (pdata && pdata->dma_channels)
dma_channels = pdata->dma_channels;
else
@@ -958,8 +963,9 @@ static int mmp_pdma_probe(struct platform_device *op)
irq_num++;
}

- pdev->phy = devm_kzalloc(pdev->dev,
- dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+ pdev->phy = devm_kcalloc(pdev->dev,
+ dma_channels, sizeof(struct mmp_pdma_chan),
+ GFP_KERNEL);
if (pdev->phy == NULL)
return -ENOMEM;

@@ -968,8 +974,8 @@ static int mmp_pdma_probe(struct platform_device *op)
if (irq_num != dma_channels) {
/* all chan share one irq, demux inside */
irq = platform_get_irq(op, 0);
- ret = devm_request_irq(pdev->dev, irq,
- mmp_pdma_int_handler, 0, "pdma", pdev);
+ ret = devm_request_irq(pdev->dev, irq, mmp_pdma_int_handler, 0,
+ "pdma", pdev);
if (ret)
return ret;
}
@@ -1044,7 +1050,7 @@ bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param)
if (chan->device->dev->driver != &mmp_pdma_driver.driver)
return false;

- c->drcmr = *(unsigned int *) param;
+ c->drcmr = *(unsigned int *)param;

return true;
}
@@ -1052,6 +1058,6 @@ EXPORT_SYMBOL_GPL(mmp_pdma_filter_fn);

module_platform_driver(mmp_pdma_driver);

-MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver");
+MODULE_DESCRIPTION("MARVELL MMP Peripheral DMA Driver");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");

[Shevchenko, Andriy]

On Sun, 2013-11-17 at 16:39 +0100, Florian Meier wrote:

> Add support for DMA controller of BCM2835 as used in the Raspberry Pi.
> Currently it only supports cyclic DMA.

Few comments below.

> +++ b/drivers/dma/bcm2835-dma.c
> @@ -0,0 +1,736 @@

> +static int bcm2835_dma_abort(void __iomem *chan_base)
> +{
> + unsigned long int cs;
> + long int timeout = 10000;
> +
> + cs = readl(chan_base + BCM2835_DMA_CS);
> + if (!(cs & BCM2835_DMA_ACTIVE))
> + return 0;
> +
> + /* Write 0 to the active bit - Pause the DMA */
> + writel(0, chan_base + BCM2835_DMA_CS);
> +
> + /* Wait for any current AXI transfer to complete */
> + while ((cs & BCM2835_DMA_ISPAUSED) && --timeout >= 0)
> + cs = readl(chan_base + BCM2835_DMA_CS);

I actually don't see timeout here. timeout means counter in your case.
Might be better to have something like

while (readl(...) & BCM2835_DMA_ISPAUSED && --timeout)
cpu_relax();

?

> + /* We'll un-pause when we set of our next DMA */
> + if (cs & BCM2835_DMA_ISPAUSED)

if (!timeout)

> + return -ETIMEDOUT;


> +
> + if (!(cs & BCM2835_DMA_ACTIVE))
> + return 0;

Duplicate code. Perhaps
static inline bool is_chan_not_active(unsigned long cs)
{
return !(cs & BCM2835_DMA_ACTIVE);
}

[]

> +static irqreturn_t bcm2835_dma_callback(int irq, void *data)
> +{

[]

> + writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);

Since it's duplicate code, perhaps

static inline void set_chan_active(void __iomem *base)
{
writel(BCM2835_DMA_ACTIVE, base + BCM2835_DMA_CS);
}

[]

> +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
> +{
> + unsigned i;

In some cases you use 'unsigned long int' for 'unsigned long', for
example, but here 'unsigned' instead of 'unsigned int'. Please, align
style with certain choice.

[]

> +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
> + dma_cookie_t cookie, struct dma_tx_state *txstate)
> +{

[]

> + } else {
> + txstate->residue = 0;

Useless assignment since dmaengine will do this for you in
dma_cookie_status.

[]

> +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
> + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
> + size_t period_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{

[]

> + /* Grab configuration */
> + if (direction == DMA_DEV_TO_MEM) {
> + dev_addr = c->cfg.src_addr;
> + dev_width = c->cfg.src_addr_width;
> + sync_type = BCM2835_DMA_S_DREQ;
> + } else if (direction == DMA_MEM_TO_DEV) {
> + dev_addr = c->cfg.dst_addr;
> + dev_width = c->cfg.dst_addr_width;
> + sync_type = BCM2835_DMA_D_DREQ;
> + } else {
> + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
> + return NULL;
> + }

You might use following as well

if (!is_slave_direction) {
dev_err(...);
return NULL;
}

if (direction == DMA_DEV_TO_MEM)
{
...
} else {
...
}

?

At least it will be aligned with what you have further in this function.

> + /* Bus width translates to the element size (ES) */
> + switch (dev_width) {
> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> + es = BCM2835_DMA_DATA_TYPE_S32;
> + break;
> + default:
> + return NULL;
> + }

So, you use switch-case on hope to extend it later, correct?

[]

> +static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
> +{
> + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
> + unsigned long flags;
> + int timeout = 1000;
> + LIST_HEAD(head);

[]

> + if (c->desc) {
> + c->desc = NULL;
> + bcm2835_dma_abort(c->chan_base);
> +
> + /* Wait for stopping */
> + while (timeout > 0) {
> + timeout--;

while (--timeout)

> + if (!(readl(c->chan_base + BCM2835_DMA_CS) &
> + BCM2835_DMA_ACTIVE))
> + break;
> +
> + cpu_relax();
> + }
> +
> + if (timeout <= 0)

if (!timeout)

[]

Perhaps

if (!chan)
goto retry;

> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> +
> + /* Set DREQ from param */
> + c->dreq = spec->args[0];
> +
> + return chan;
> + }
> +
> + goto retry;
> +}

> +static int bcm2835_dma_probe(struct platform_device *pdev)
> +{
> + struct bcm2835_dmadev *od;
> + struct resource *res;
> + void __iomem *base;
> + int rc;
> + int i;
> + int irq;
> + uint32_t chans_available;

Why uint32_t?

[]

> + if (pdev->dev.of_node) {

Perhaps

if (!...of_node) {
...
return -EINVAL;

}

> + /* Request DMA channel mask from device tree */
> + if (of_property_read_u32(pdev->dev.of_node,
> + "brcm,dma-channel-mask",
> + &chans_available)) {
> + dev_err(&pdev->dev, "Failed to get channel mask\n");
> + bcm2835_dma_free(od);
> + return -EINVAL;
> + }
> + } else {
> + dev_err(&pdev->dev, "Failed to get channel mask. No device tree.\n");
> + bcm2835_dma_free(od);
> + return -EINVAL;
> + }

> + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
> +
> + if (pdev->dev.of_node) {

Does it make sense?

> + /* Device-tree DMA controller registration */
> + rc = of_dma_controller_register(pdev->dev.of_node,
> + bcm2835_dma_xlate, od);
> + if (rc) {
> + dev_err(&pdev->dev, "Failed to register DMA controller\n");
> + bcm2835_dma_free(od);
> + return rc;

goto err_no_dma;

> + }
> + }
> +
> + rc = dma_async_device_register(&od->ddev);
> + if (rc) {
> + dev_err(&pdev->dev,
> + "Failed to register slave DMA engine device: %d\n", rc);
> + bcm2835_dma_free(od);
> + return rc;

goto err_no_dma;

> + }
> +
> + dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");

> + return rc;

return 0;

err_no_dma:
bcm2835_dma_free(od);
return rc;

[Florian Meier]

Thank you! Few comments below.

> []
>> +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
>> + dma_cookie_t cookie, struct dma_tx_state *txstate)
>> +{
>
> []
>
>> + } else {
>> + txstate->residue = 0;
>
> Useless assignment since dmaengine will do this for you in
> dma_cookie_status.

I agree that it is useless, but I think otherwise it might be concealed
that there is a third case left that uses a residue of 0. Do you think a
comment is better? E.g.:

+ } else {
+ /* residue = 0 per default */

>> + /* Bus width translates to the element size (ES) */
>> + switch (dev_width) {
>> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
>> + es = BCM2835_DMA_DATA_TYPE_S32;
>> + break;
>> + default:
>> + return NULL;
>> + }
>
> So, you use switch-case on hope to extend it later, correct?

Yes, there is a S128 case left, but that is not implemented yet.

>> +static int bcm2835_dma_probe(struct platform_device *pdev)
>> +{
>> + struct bcm2835_dmadev *od;
>> + struct resource *res;
>> + void __iomem *base;
>> + int rc;
>> + int i;
>> + int irq;
>> + uint32_t chans_available;
>
> Why uint32_t?

Because it is a bit mask of fixed length that directly comes from the
firmware.

>> + /* Request DMA channel mask from device tree */
>> + if (of_property_read_u32(pdev->dev.of_node,
>> + "brcm,dma-channel-mask",
>> + &chans_available)) {
>> + dev_err(&pdev->dev, "Failed to get channel mask\n");
>> + bcm2835_dma_free(od);
>> + return -EINVAL;
>> + }
>> + } else {
>> + dev_err(&pdev->dev, "Failed to get channel mask. No device tree.\n");
>> + bcm2835_dma_free(od);
>> + return -EINVAL;
>> + }
>
>> + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
>> +
>> + if (pdev->dev.of_node) {
>
> Does it make sense?

There was already a discussion about that in PATCHv4. It should be
possible to add board file initialization later with few patching.
Although, maybe this will not be relevant anymore, because device tree
support of this platform is getting better more and more.

[Florian Meier]

>>>> +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
>>>> + dma_cookie_t cookie, struct dma_tx_state *txstate)
>>>> +{
>>>
>>> []
>>>
>>>> + } else {
>>>> + txstate->residue = 0;
>>>
>>> Useless assignment since dmaengine will do this for you in
>>> dma_cookie_status.
>>
>> I agree that it is useless, but I think otherwise it might be concealed
>> that there is a third case left that uses a residue of 0. Do you think a
>> comment is better? E.g.:
>>
>> + } else {
>> + /* residue = 0 per default */
>

> I think like in many other DMA drivers either you have separate function
> to get residue, which returns 0, or just not include this case.

You mean like in the omap-dma.c? ;-P

>>>> +static int bcm2835_dma_probe(struct platform_device *pdev)
>>>> +{
>

>>>> + uint32_t chans_available;
>>>
>>> Why uint32_t?
>>
>> Because it is a bit mask of fixed length that directly comes from the
>> firmware.
>

> Like one already told you in your i2s patch, please, change that to
> corresponding u* value, namely u32.

I have no problem with changing that, but why?

[Andy Shevchenko]

On Mon, 2013-11-18 at 13:16 +0100, Florian Meier wrote:
> Thank you! Few comments below.

See my answers below.

> >> +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
> >> + dma_cookie_t cookie, struct dma_tx_state *txstate)
> >> +{
> >
> > []
> >
> >> + } else {
> >> + txstate->residue = 0;
> >
> > Useless assignment since dmaengine will do this for you in
> > dma_cookie_status.
>
> I agree that it is useless, but I think otherwise it might be concealed
> that there is a third case left that uses a residue of 0. Do you think a
> comment is better? E.g.:
>
> + } else {
> + /* residue = 0 per default */

I think like in many other DMA drivers either you have separate function
to get residue, which returns 0, or just not include this case.

> >> +static int bcm2835_dma_probe(struct platform_device *pdev)
> >> +{

> >> + uint32_t chans_available;
> >
> > Why uint32_t?
>
> Because it is a bit mask of fixed length that directly comes from the
> firmware.

Like one already told you in your i2s patch, please, change that to
corresponding u* value, namely u32.

--
Andy Shevchenko <andriy.s...@linux.intel.com>
Intel Finland Oy

[Mark Rutland]

The format of the cells is a property of the interrupt parent, not of
the DMA controller. It shouldn't be described here.

> +- #dma-cells: Must be <1>, used to represent the number of integer cells in
> + the dmas property of client devices.

A brief description of the set of sane values of the dma-specifier cell
would be better.

How many channels does the DMA controller have?

> +- brcm,dma-channel-mask: Bit mask representing the channels
> + not used by the firmware.

Which bits correspond to which channels?

How many channels are likely to be reserved out of how many in total?

Are they likely to be an arbitrary set, or some contiguous range?

> +
> +Example:
> +
> +dma: dma@7e007000 {
> + compatible = "brcm,bcm2835-dma";
> + reg = <0x7e007000 0xf00>;
> + interrupts = <1 16
> + 1 17
> + 1 18
> + 1 19
> + 1 20
> + 1 21
> + 1 22
> + 1 23
> + 1 24
> + 1 25
> + 1 26
> + 1 27
> + 1 28>;

Please bracket these individually.

> +
> + #dma-cells = <1>;
> + brcm,dma-channel-mask = <0x7f35>;
> +};
> +
> +DMA clients connected to the BCM2835 DMA controller must use the format
> +described in the dma.txt file, using a two-cell specifier for each channel:
> +a phandle plus one integer cells.
> +The two cells in order are:
> +
> +1. A phandle pointing to the DMA controller.
> +2. The DREQ number.

This description is unnecessary, and technically wrong (the phandle
isn't part of the specifier, as the specifier goes with the phandle).

> +
> +Example:
> +
> +bcm2835_i2s: i2s@7e203000 {
> + compatible = "brcm,bcm2835-i2s";
> + reg = < 0x7e203000 0x20
> + 0x7e101098 0x02>;
> +
> + dmas = <&dma 2
> + &dma 3>;

Brackets please.

[...]

> +struct bcm2835_dma_cb {
> + uint32_t info;
> + uint32_t src;
> + uint32_t dst;
> + uint32_t length;
> + uint32_t stride;
> + uint32_t next;
> + uint32_t pad[2];

s/uint32_t/u32/ here and elsewhere.

[...]

> +static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
> +{
> + struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
> + struct bcm2835_desc *d;
> +
> + if (!vd) {
> + c->desc = NULL;
> + return;
> + }
> +
> + list_del(&vd->node);
> +
> + c->desc = d = to_bcm2835_dma_desc(&vd->tx);
> +
> + dsb(); /* ARM data synchronization (push) operation */

We all know what a dsb is. What you should explain is _why_ the dsb is
here. As this is sat under drivers, it would be nicer to use an
architecture generic barrier rather than dsb() directly.

Better explanation please.

> + writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
> +
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
> +{
> + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
> +
> + dev_dbg(c->vc.chan.device->dev,
> + "Allocating DMA channel %i\n", c->ch);

Why not %d? It's far more common...


[...]

> + if (pdev->dev.of_node) {
> + /* Request DMA channel mask from device tree */
> + if (of_property_read_u32(pdev->dev.of_node,
> + "brcm,dma-channel-mask",
> + &chans_available)) {
> + dev_err(&pdev->dev, "Failed to get channel mask\n");
> + bcm2835_dma_free(od);
> + return -EINVAL;
> + }

As of_property_read_u32 has an implicit check on np, you don't need to
first check pdev->dev.of_node.

> + } else {
> + dev_err(&pdev->dev, "Failed to get channel mask. No device tree.\n");
> + bcm2835_dma_free(od);
> + return -EINVAL;
> + }
> +
> + /* Do not use the FIQ and BULK channels */
> + chans_available &= ~0xD;

A couple of #defines would be nice, along with an explanation as to
why...

Thanks,
Mark.

[Russell King - ARM Linux]

On Mon, Nov 18, 2013 at 04:30:17PM +0200, Andy Shevchenko wrote:
> On Mon, 2013-11-18 at 13:16 +0100, Florian Meier wrote:
> > >> + uint32_t chans_available;
> > >
> > > Why uint32_t?
> >
> > Because it is a bit mask of fixed length that directly comes from the
> > firmware.
>
> Like one already told you in your i2s patch, please, change that to
> corresponding u* value, namely u32.

There's no problem with uint32_t vs u32 - either will do. u32 is the
pre-stdint.h Linux definition of a 32-bit unsigned integer. There's
no reason why uint32_t isn't perfectly acceptable. It's a matter of
author taste which gets used. (Except where modifications are to an
existing chunk of code using one or the other - where consistency then
matters more.)

[Mark Rutland]

On Mon, Nov 18, 2013 at 02:54:00PM +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 18, 2013 at 04:30:17PM +0200, Andy Shevchenko wrote:
> > On Mon, 2013-11-18 at 13:16 +0100, Florian Meier wrote:
> > > >> + uint32_t chans_available;
> > > >
> > > > Why uint32_t?
> > >
> > > Because it is a bit mask of fixed length that directly comes from the
> > > firmware.
> >
> > Like one already told you in your i2s patch, please, change that to
> > corresponding u* value, namely u32.
>
> There's no problem with uint32_t vs u32 - either will do. u32 is the
> pre-stdint.h Linux definition of a 32-bit unsigned integer. There's
> no reason why uint32_t isn't perfectly acceptable. It's a matter of
> author taste which gets used. (Except where modifications are to an
> existing chunk of code using one or the other - where consistency then
> matters more.)

Sorry for being a source of confusion here. I won't push this point in
future.

Thanks,
Mark.

[Joe Perches]

On Mon, 2013-11-18 at 14:54 +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 18, 2013 at 04:30:17PM +0200, Andy Shevchenko wrote:
> > On Mon, 2013-11-18 at 13:16 +0100, Florian Meier wrote:
> > > >> + uint32_t chans_available;
> > > >
> > > > Why uint32_t?
> > >
> > > Because it is a bit mask of fixed length that directly comes from the
> > > firmware.
> >
> > Like one already told you in your i2s patch, please, change that to
> > corresponding u* value, namely u32.
>
> There's no problem with uint32_t vs u32 - either will do. u32 is the
> pre-stdint.h Linux definition of a 32-bit unsigned integer. There's
> no reason why uint32_t isn't perfectly acceptable. It's a matter of
> author taste which gets used. (Except where modifications are to an
> existing chunk of code using one or the other - where consistency then
> matters more.)

https://lkml.org/lkml/2006/5/2/258

[Vinod Koul]

On Sun, Nov 17, 2013 at 12:12:56PM -0800, Joe Perches wrote:
> Neaten code used as a template for other drivers.
> Make the code more consistent with kernel styles.
>
> o Convert #defines with (1<<foo) to BIT(foo)
> o Alignment wrapping
> o Logic inversions to put return at end of functions
> o Convert devm_kzalloc with multiply to devm_kcalloc
> o typo of Peripheral fix
>
> Signed-off-by: Joe Perches <j...@perches.com>
> ---
> > At least, the code is directly taken from mmp_pdma.c ;-)
>
> Well, maybe the template code should be updated if there
> are going to be more of these.
>
> Uncompiled/untested.

Compile tested and applied.

BUT you should not have hijacked the thread and sent this patch on a different
chain!

--
~Vinod

[Gene Anderson]

Group:

This is a request to augment with comments the
DREQ explanation in the Broadcom BCM2835
pdf on page 61 regarding DMA peripheral
mapping. Specifically, how to identify a pin on the 26
pin
header to use for DMA reads. More specifically,
if a clock signal,
like GPCLK0 is output to the peripheral device
(like an A/D converter) how we specify PERMAP in the
DMA TI register. Your users would be infinitely grateful.

thank you,