Make - mulitple targets but from lists

[John Hetherington]

#
# Can anyone help me ?
#
# I need this makefile to generate the following output,
#
# Created r.x.c from x.c
# Created s.x.c from x.c
# Created t.x.c from x.c
# Created r.y.c from y.c
# Created s.y.c from y.c
# Created t.y.c from y.c
#
# but only using the contents of the two lists, SRCS and PREFIXES.
#
# Just create dummy files for those files in the SRCS list.
# e.g. touch x.c y.c
#
# Thanx in advance.
#
# John Hetherington (j...@eagpde.co.uk)
#

SRCS = x.c y.c
PREFIXES = r s t
ECHO = /usr/ucb/echo

A = $(foreach src, $(SRCS), $(foreach prefix, $(PREFIXES), $(addprefix
$(prefix)., $(src) )))

install: $(A)

$(A): %: $(src)
@$(ECHO) Created $@ from $(src)

[Paul D. Smith]

%% John Hetherington <j...@eagpde.co.uk> writes:

jh> # Can anyone help me ?
jh> #
jh> # I need this makefile to generate the following output,
jh> #
jh> # Created r.x.c from x.c
jh> # Created s.x.c from x.c
jh> # Created t.x.c from x.c
jh> # Created r.y.c from y.c
jh> # Created s.y.c from y.c
jh> # Created t.y.c from y.c
jh> #
jh> # but only using the contents of the two lists, SRCS and PREFIXES.

jh> SRCS = x.c y.c
jh> PREFIXES = r s t

I don't see any excellent way to do it. However, here are two
alternatives:

The first uses pattern rules. However, remember that a pattern rule
with multiple patterns for targets means that a single invocation of
this rule builds all the targets; that's not actually what you want but
there's no way to avoid it, so you'll have to really do that:

.SUFFIXES:

SRCS = x.c y.c
PREFIXES = r s t

PATTERN = $(foreach p,$(PREFIXES),$(p).%)

ALL = $(foreach p,$(PREFIXES),$(foreach s,$(SRCS),$(p).$(s)))

all: $(ALL)

$(PATTERN):: %
@for p in $(PREFIXES); do \
echo Created $$p.$< from $<; \
done

Here we use a shell loop in the pattern rule to run the command once per
prefix.

The other option is to use a constructed makefile, something like this:

.SUFFIXES:

SRCS = x.c y.c
PREFIXES = r s t

COMMAND = @echo Created $$@ from $$<

ALL = $(foreach s,$(SRCS),$(foreach p,$(PREFIXES),$(p).$(s)))

all: $(ALL)

Makefile.inc: Makefile
@rm -f $@; \
for p in $(PREFIXES); do \
echo $$p.% :: %\; '$(COMMAND)'>>$@; \
done

-include Makefile.inc

This one builds a helper makefile containing a pattern rule for each
element of the PREFIXES list.

The trick to this one is knowing when to rebuild Makefile.inc; here I
have it rebuilding whenever Makefile itself changes, which is certainly
good enough since if you change the contents of PREFIXES the Makefile
will have to change, but it's slightly overkill since lots of other
changes will cause a rebuild of Makefile.inc... but since it's quite
trivial to make it this is probably good enough.

Take your pick...

--
-------------------------------------------------------------------------------
Paul D. Smith <psm...@baynetworks.com> Network Management Development
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
-------------------------------------------------------------------------------
These are my opinions--Bay Networks takes no responsibility for them.