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Thierry Reding  
View profile  
 More options Nov 9 2012, 8:59 am
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Fri, 09 Nov 2012 13:59:57 UTC
Local: Fri, Nov 9 2012 8:59 am
Subject: [PATCH 0/2] NVIDIA Tegra DRM driver
Hi,

This small set of patches adds support for the host1x and a subset of
the display controller hardware available on NVIDIA Tegra SoCs.

The first patch makes the RGB output available, which is directly driven
by its parent display controller and usually connected to an LVDS bridge
in embedded and notebook applications.

The second patch adds support for the HDMI output which can be driven by
any of the two display controllers.

This set of patches uses the GEM/CMA and KMS/FB helpers by Sascha Hauer
and Lars-Peter Clausen respectively.

Note that the driver is fully functional, but a few things are still
missing from this series because they depend on other patches that have
not been included in mainline yet. One such series is Steffen Trumtrar's
display helper series that allows the display modes to be defined within
the device tree, which comes in handy for embedded applications. What's
also missing from this series is the glue to wire up a backlight device
with a DRM connector so that the backlight can be switched on and off at
the proper time. I will submit incremental patches as the dependencies
make it into Linus' tree.

There is a full set of patches available in the tegra/next branch of my
repository on gitorious[0]. I know that a few people have already tested
the code on that branch, which has been very helpful in ironing out some
of the final details.

I fully realize that this is awfully late, but I still hope to get this
in for 3.8. I've talked about this with David Airlie and he said if I
can get the patches reviewed sometime before 3.7-rc6 or 3.7-rc7 by some
people of the embedded DRM crowd he may take them into the 3.8 merge
window. That would leave about 2 weeks for review, so if anybody could
find the time to look at this code that'd be great.

During the development of this series I've received a lot of feedback
and many helpful suggestions from the people at NVIDIA, so I owe them
big thanks.

Thierry

[0]: git://gitorious.org/thierryreding/linux.git

Thierry Reding (2):
  drm: Add NVIDIA Tegra20 support
  drm: tegra: Add HDMI support

 .../bindings/gpu/drm/nvidia,tegra20-host1x.txt     |  191 +++
 drivers/gpu/drm/Kconfig                            |    2 +
 drivers/gpu/drm/Makefile                           |    1 +
 drivers/gpu/drm/tegra/Kconfig                      |   23 +
 drivers/gpu/drm/tegra/Makefile                     |    7 +
 drivers/gpu/drm/tegra/dc.c                         |  817 +++++++++++++
 drivers/gpu/drm/tegra/dc.h                         |  384 ++++++
 drivers/gpu/drm/tegra/drm.c                        |  115 ++
 drivers/gpu/drm/tegra/drm.h                        |  235 ++++
 drivers/gpu/drm/tegra/fb.c                         |   56 +
 drivers/gpu/drm/tegra/hdmi.c                       | 1290 ++++++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.h                       |  575 +++++++++
 drivers/gpu/drm/tegra/host1x.c                     |  321 +++++
 drivers/gpu/drm/tegra/output.c                     |  275 +++++
 drivers/gpu/drm/tegra/rgb.c                        |  200 +++
 15 files changed, 4492 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt
 create mode 100644 drivers/gpu/drm/tegra/Kconfig
 create mode 100644 drivers/gpu/drm/tegra/Makefile
 create mode 100644 drivers/gpu/drm/tegra/dc.c
 create mode 100644 drivers/gpu/drm/tegra/dc.h
 create mode 100644 drivers/gpu/drm/tegra/drm.c
 create mode 100644 drivers/gpu/drm/tegra/drm.h
 create mode 100644 drivers/gpu/drm/tegra/fb.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.h
 create mode 100644 drivers/gpu/drm/tegra/host1x.c
 create mode 100644 drivers/gpu/drm/tegra/output.c
 create mode 100644 drivers/gpu/drm/tegra/rgb.c

--
1.8.0

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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Thierry Reding
Thierry Reding  
View profile  
 More options Nov 9 2012, 9:00 am
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Fri, 09 Nov 2012 14:00:15 UTC
Local: Fri, Nov 9 2012 9:00 am
Subject: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.

Signed-off-by: Thierry Reding <thierry.red...@avionic-design.de>
---
 .../bindings/gpu/drm/nvidia,tegra20-host1x.txt     | 191 +++++
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/tegra/Kconfig                      |  23 +
 drivers/gpu/drm/tegra/Makefile                     |   7 +
 drivers/gpu/drm/tegra/dc.c                         | 817 +++++++++++++++++++++
 drivers/gpu/drm/tegra/dc.h                         | 384 ++++++++++
 drivers/gpu/drm/tegra/drm.c                        | 115 +++
 drivers/gpu/drm/tegra/drm.h                        | 233 ++++++
 drivers/gpu/drm/tegra/fb.c                         |  56 ++
 drivers/gpu/drm/tegra/host1x.c                     | 313 ++++++++
 drivers/gpu/drm/tegra/output.c                     | 275 +++++++
 drivers/gpu/drm/tegra/rgb.c                        | 200 +++++
 13 files changed, 2617 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt
 create mode 100644 drivers/gpu/drm/tegra/Kconfig
 create mode 100644 drivers/gpu/drm/tegra/Makefile
 create mode 100644 drivers/gpu/drm/tegra/dc.c
 create mode 100644 drivers/gpu/drm/tegra/dc.h
 create mode 100644 drivers/gpu/drm/tegra/drm.c
 create mode 100644 drivers/gpu/drm/tegra/drm.h
 create mode 100644 drivers/gpu/drm/tegra/fb.c
 create mode 100644 drivers/gpu/drm/tegra/host1x.c
 create mode 100644 drivers/gpu/drm/tegra/output.c
 create mode 100644 drivers/gpu/drm/tegra/rgb.c

diff --git a/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt
new file mode 100644
index 0000000..b4fa934
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt
@@ -0,0 +1,191 @@
+NVIDIA Tegra host1x
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-host1x"
+- reg: Physical base address and length of the controller's registers.
+- interrupts: The interrupt outputs from the controller.
+- #address-cells: The number of cells used to represent physical base addresses
+  in the host1x address space. Should be 1.
+- #size-cells: The number of cells used to represent the size of an address
+  range in the host1x address space. Should be 1.
+- ranges: The mapping of the host1x address space to the CPU address space.
+
+The host1x top-level node defines a number of children, each representing one
+of the following host1x client modules:
+
+- mpe: video encoder
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-mpe"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- vi: video input
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-vi"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- epp: encoder pre-processor
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-epp"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- isp: image signal processor
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-isp"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- gr2d: 2D graphics engine
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-gr2d"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- gr3d: 3D graphics engine
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-gr3d"
+  - reg: Physical base address and length of the controller's registers.
+
+- dc: display controller
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-dc"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+  Each display controller node has a child node, named "rgb", that represents
+  the RGB output associated with the controller. It can take the following
+  optional properties:
+  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+  - nvidia,edid: supplies a binary EDID blob
+
+- hdmi: High Definition Multimedia Interface
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-hdmi"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+  - vdd-supply: regulator for supply voltage
+  - pll-supply: regulator for PLL
+
+  Optional properties:
+  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+  - nvidia,edid: supplies a binary EDID blob
+
+- tvo: TV encoder output
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-tvo"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- dsi: display serial interface
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-dsi"
+  - reg: Physical base address and length of the controller's registers.
+
+Example:
+
+/ {
+       ...
+
+       host1x {
+               compatible = "nvidia,tegra20-host1x", "simple-bus";
+               reg = <0x50000000 0x00024000>;
+               interrupts = <0 65 0x04   /* mpcore syncpt */
+                             0 67 0x04>; /* mpcore general */
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               ranges = <0x54000000 0x54000000 0x04000000>;
+
+               mpe {
+                       compatible = "nvidia,tegra20-mpe";
+                       reg = <0x54040000 0x00040000>;
+                       interrupts = <0 68 0x04>;
+               };
+
+               vi {
+                       compatible = "nvidia,tegra20-vi";
+                       reg = <0x54080000 0x00040000>;
+                       interrupts = <0 69 0x04>;
+               };
+
+               epp {
+                       compatible = "nvidia,tegra20-epp";
+                       reg = <0x540c0000 0x00040000>;
+                       interrupts = <0 70 0x04>;
+               };
+
+               isp {
+                       compatible = "nvidia,tegra20-isp";
+                       reg = <0x54100000 0x00040000>;
+                       interrupts = <0 71 0x04>;
+               };
+
+               gr2d {
+                       compatible = "nvidia,tegra20-gr2d";
+                       reg = <0x54140000 0x00040000>;
+                       interrupts = <0 72 0x04>;
+               };
+
+               gr3d {
+                       compatible = "nvidia,tegra20-gr3d";
+                       reg = <0x54180000 0x00040000>;
+               };
+
+               dc@54200000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54200000 0x00040000>;
+                       interrupts = <0 73 0x04>;
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               dc@54240000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54240000 0x00040000>;
+                       interrupts = <0 74 0x04>;
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               hdmi {
+                       compatible = "nvidia,tegra20-hdmi";
+                       reg = <0x54280000 0x00040000>;
+                       interrupts = <0 75 0x04>;
+                       status = "disabled";
+               };
+
+               tvo {
+                       compatible = "nvidia,tegra20-tvo";
+                       reg = <0x542c0000 0x00040000>;
+                       interrupts = <0 76 0x04>;
+                       status = "disabled";
+               };
+
+               dsi {
+                       compatible = "nvidia,tegra20-dsi";
+                       reg = <0x54300000 0x00040000>;
+                       status = "disabled";
+               };
+       };
+
+       ...
+};
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 18321b68b..983201b 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -210,3 +210,5 @@ source "drivers/gpu/drm/mgag200/Kconfig"
 source "drivers/gpu/drm/cirrus/Kconfig"

 source "drivers/gpu/drm/shmobile/Kconfig"
+
+source "drivers/gpu/drm/tegra/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2ff5cef..0bfda06 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -48,4 +48,5 @@ obj-$(CONFIG_DRM_GMA500) += gma500/
 obj-$(CONFIG_DRM_UDL) += udl/
 obj-$(CONFIG_DRM_AST) += ast/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
+obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-y                  += i2c/
diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
new file mode 100644
index 0000000..be1daf7
--- /dev/null
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -0,0 +1,23 @@
+config DRM_TEGRA
+       tristate "NVIDIA Tegra DRM"
+       depends on DRM && OF && ARCH_TEGRA
+       select DRM_KMS_HELPER
+       select DRM_GEM_CMA_HELPER
+       select DRM_KMS_CMA_HELPER
+       select FB_CFB_FILLRECT
+       select FB_CFB_COPYAREA
+       select FB_CFB_IMAGEBLIT
+       help
+         Choose this option if you have an NVIDIA Tegra SoC.
+
+         To compile this driver as a module, choose M here: the module
+         will be called tegra-drm.
+
+if DRM_TEGRA
+
+config DRM_TEGRA_DEBUG
+       bool "NVIDIA Tegra DRM debug support"
+       help
+         Say yes here to enable debugging support.
+
+endif
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
new file mode 100644
index 0000000..624a807
--- /dev/null
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
+
+tegra-drm-y := drm.o fb.o dc.o host1x.o
+tegra-drm-y += output.o rgb.o
+
+obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
new file mode 100644
index 0000000..213a729
--- /dev/null
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -0,0 +1,817 @@
+/*
+ * Copyright (C) 2012 Avionic Design GmbH
+ * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+ ...

read more »


 
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Discussion subject changed to "drm: tegra: Add HDMI support" by Thierry Reding
Thierry Reding  
View profile  
 More options Nov 9 2012, 9:00 am
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Fri, 09 Nov 2012 14:00:34 UTC
Local: Fri, Nov 9 2012 9:00 am
Subject: [PATCH 2/2] drm: tegra: Add HDMI support
This commit adds support for the HDMI output on the Tegra20 SoC. Only
one such output is available, but it can be driven by either of the two
display controllers.

A lot of work on this patch has been contributed by NVIDIA's Mark Zhang
<ma...@nvidia.com> and many other people at NVIDIA were very helpful in
getting the HDMI support and surrounding infrastructure to work.

Signed-off-by: Thierry Reding <thierry.red...@avionic-design.de>
---
 drivers/gpu/drm/tegra/Makefile |    2 +-
 drivers/gpu/drm/tegra/drm.h    |    2 +
 drivers/gpu/drm/tegra/hdmi.c   | 1290 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.h   |  575 ++++++++++++++++++
 drivers/gpu/drm/tegra/host1x.c |    8 +
 5 files changed, 1876 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/tegra/hdmi.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.h

diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 624a807..80f73d1 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -2,6 +2,6 @@ ccflags-y := -Iinclude/drm
 ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG

 tegra-drm-y := drm.o fb.o dc.o host1x.o
-tegra-drm-y += output.o rgb.o
+tegra-drm-y += output.o rgb.o hdmi.o

 obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 7334b68..03cb06f 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -133,6 +133,7 @@ struct tegra_output_ops {

 enum tegra_output_type {
        TEGRA_OUTPUT_RGB,
+       TEGRA_OUTPUT_HDMI,
 };

 struct tegra_output {
@@ -227,6 +228,7 @@ extern int tegra_drm_fb_init(struct drm_device *drm);
 extern void tegra_drm_fb_exit(struct drm_device *drm);

 extern struct platform_driver tegra_host1x_driver;
+extern struct platform_driver tegra_hdmi_driver;
 extern struct platform_driver tegra_dc_driver;
 extern struct drm_driver tegra_drm_driver;

diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
new file mode 100644
index 0000000..907a855
--- /dev/null
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (C) 2012 Avionic Design GmbH
+ * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/clk.h>
+
+#include "hdmi.h"
+#include "drm.h"
+#include "dc.h"
+
+struct tegra_hdmi {
+       struct host1x_client client;
+       struct tegra_output output;
+       struct device *dev;
+
+       struct regulator *vdd;
+       struct regulator *pll;
+
+       void __iomem *regs;
+       unsigned int irq;
+
+       struct clk *clk_parent;
+       struct clk *clk;
+
+       unsigned int audio_source;
+       unsigned int audio_freq;
+       bool stereo;
+       bool dvi;
+
+       struct dentry *debugfs;
+};
+
+static inline struct tegra_hdmi *
+host1x_client_to_hdmi(struct host1x_client *client)
+{
+       return container_of(client, struct tegra_hdmi, client);
+}
+
+static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
+{
+       return container_of(output, struct tegra_hdmi, output);
+}
+
+#define HDMI_AUDIOCLK_FREQ 216000000
+#define HDMI_REKEY_DEFAULT 56
+
+enum {
+       AUTO = 0,
+       SPDIF,
+       HDA,
+};
+
+static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
+                                            unsigned long reg)
+{
+       return readl(hdmi->regs + (reg << 2));
+}
+
+static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
+                                    unsigned long reg)
+{
+       writel(val, hdmi->regs + (reg << 2));
+}
+
+struct tegra_hdmi_audio_config {
+       unsigned int pclk;
+       unsigned int n;
+       unsigned int cts;
+       unsigned int aval;
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
+       {  25200000, 4096,  25200, 24000 },
+       {  27000000, 4096,  27000, 24000 },
+       {  74250000, 4096,  74250, 24000 },
+       { 148500000, 4096, 148500, 24000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
+       {  25200000, 5880,  26250, 25000 },
+       {  27000000, 5880,  28125, 25000 },
+       {  74250000, 4704,  61875, 20000 },
+       { 148500000, 4704, 123750, 20000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
+       {  25200000, 6144,  25200, 24000 },
+       {  27000000, 6144,  27000, 24000 },
+       {  74250000, 6144,  74250, 24000 },
+       { 148500000, 6144, 148500, 24000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
+       {  25200000, 11760,  26250, 25000 },
+       {  27000000, 11760,  28125, 25000 },
+       {  74250000,  9408,  61875, 20000 },
+       { 148500000,  9408, 123750, 20000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
+       {  25200000, 12288,  25200, 24000 },
+       {  27000000, 12288,  27000, 24000 },
+       {  74250000, 12288,  74250, 24000 },
+       { 148500000, 12288, 148500, 24000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
+       {  25200000, 23520,  26250, 25000 },
+       {  27000000, 23520,  28125, 25000 },
+       {  74250000, 18816,  61875, 20000 },
+       { 148500000, 18816, 123750, 20000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
+       {  25200000, 24576,  25200, 24000 },
+       {  27000000, 24576,  27000, 24000 },
+       {  74250000, 24576,  74250, 24000 },
+       { 148500000, 24576, 148500, 24000 },
+       {         0,     0,      0,     0 },
+};
+
+struct tmds_config {
+       unsigned int pclk;
+       u32 pll0;
+       u32 pll1;
+       u32 pe_current;
+       u32 drive_current;
+};
+
+static const struct tmds_config tegra2_tmds_config[] = {
+       { /* 480p modes */
+               .pclk = 27000000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+               .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_0_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       }, { /* 720p modes */
+               .pclk = 74250000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_6_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       }, { /* 1080p modes */
+               .pclk = UINT_MAX,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_6_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       },
+};
+
+static const struct tmds_config tegra3_tmds_config[] = {
+       { /* 480p modes */
+               .pclk = 27000000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+               .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_0_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+       }, { /* 720p modes */
+               .pclk = 74250000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_5_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+       }, { /* 1080p modes */
+               .pclk = UINT_MAX,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_5_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+       },
+};
+
+static const struct tegra_hdmi_audio_config * ...

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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Rob Clark
Rob Clark  
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 More options Nov 9 2012, 10:21 am
Newsgroups: fa.linux.kernel
From: Rob Clark <robdcl...@gmail.com>
Date: Fri, 09 Nov 2012 15:21:05 UTC
Local: Fri, Nov 9 2012 10:21 am
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On Fri, Nov 9, 2012 at 7:59 AM, Thierry Reding

...

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Discussion subject changed to "drm: tegra: Add HDMI support" by Rafał Miłecki
Rafał Miłecki  
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 More options Nov 9 2012, 10:45 am
Newsgroups: fa.linux.kernel
From: Rafał Miłecki <zaj...@gmail.com>
Date: Fri, 09 Nov 2012 15:45:44 UTC
Local: Fri, Nov 9 2012 10:45 am
Subject: Re: [PATCH 2/2] drm: tegra: Add HDMI support
2012/11/9 Thierry Reding <thierry.red...@avionic-design.de>:

I was told it won't work on different endian devices. See
[RFC][PATCH] drm/radeon/hdmi: define struct for AVI infoframe
http://lists.freedesktop.org/archives/dri-devel/2012-May/022544.html

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Christian König  
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 More options Nov 9 2012, 11:01 am
Newsgroups: fa.linux.kernel
From: Christian König <deathsim...@vodafone.de>
Date: Fri, 09 Nov 2012 16:01:25 UTC
Local: Fri, Nov 9 2012 11:01 am
Subject: Re: [PATCH 2/2] drm: tegra: Add HDMI support
On 09.11.2012 16:45, Rafał Miłecki wrote:

Yeah, that's indeed true. And honestly adding just another
implementation of the HDMI info frames sounds like somebody should
finally sit down and implement it in a common drm_hdmi.c

Regards,
Christian.

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Rafał Miłecki  
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 More options Nov 9 2012, 11:04 am
Newsgroups: fa.linux.kernel
From: Rafał Miłecki <zaj...@gmail.com>
Date: Fri, 09 Nov 2012 16:04:17 UTC
Local: Fri, Nov 9 2012 11:04 am
Subject: Re: [PATCH 2/2] drm: tegra: Add HDMI support
2012/11/9 Christian König <deathsim...@vodafone.de>:

> On 09.11.2012 16:45, Rafał Miłecki wrote:
>> I was told it won't work on different endian devices. See
>> [RFC][PATCH] drm/radeon/hdmi: define struct for AVI infoframe
>> http://lists.freedesktop.org/archives/dri-devel/2012-May/022544.html

> Yeah, that's indeed true. And honestly adding just another implementation of
> the HDMI info frames sounds like somebody should finally sit down and
> implement it in a common drm_hdmi.c

Agree.

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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Rob Clark
Rob Clark  
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 More options Nov 9 2012, 11:27 am
Newsgroups: fa.linux.kernel
From: Rob Clark <robdcl...@gmail.com>
Date: Fri, 09 Nov 2012 16:27:00 UTC
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On Fri, Nov 9, 2012 at 10:00 AM, Thierry Reding

yeah, no separate directories.. but you could use the void *arg.  It
is a bit awkward for dealing with multiple subdevices, we have the
same issue w/ omapdrm where dmm is a separate subdevice (and
dsi/dpi/hdmi/etc too shortly, as we merge omapdss and omapdrm).

But I guess better handling in drm for subdevices would help a lot of
the SoC platforms.  Maybe something that I'll give some more thought
later after the atomic pageflip/modeset stuff is sorted.

>> > +/* synchronization points */
>> > +#define SYNCPT_VBLANK0 26
>> > +#define SYNCPT_VBLANK1 27

>> maybe these should be in dc.h?  Seems like these are related to the dc hw block?

> Yes, they could go into dc.h. This is one of the things that is likely
> to change at some point as more of the host1x support is added, which is
> where those syncpts are actually used.

hmm, are these values defined by the hw?  They look like register
offsets into the DC block?

ahh, ok, I guess if DRM is torn down on first unregister, then you
shouldn't be hitting issues.  I wasn't sure if the intention was to be
able to load/unload clients independently (such as building them as
separate modules eventually)

BR,
-R

> I don't believe there's an issue here. It's precisely what I've been
> testing for a while, always making sure that when built as a module it
> can properly be unloaded.

> That said it probably won't matter very much since on Tegra all drivers
> are usually builtin, so none of this may even be used in the end.

> Thanks for the quick review.

> Thierry

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Stephen Warren  
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 More options Nov 9 2012, 5:28 pm
Newsgroups: fa.linux.kernel
From: Stephen Warren <swar...@wwwdotorg.org>
Date: Fri, 09 Nov 2012 22:28:14 UTC
Local: Fri, Nov 9 2012 5:28 pm
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On 11/09/2012 06:59 AM, Thierry Reding wrote:

> This commit adds a KMS driver for the Tegra20 SoC. This includes basic
> support for host1x and the two display controllers found on the Tegra20
> SoC. Each display controller can drive a separate RGB/LVDS output.
> diff --git a/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt
> new file mode 100644
> index 0000000..b4fa934
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/drm/nvidia,tegra20-host1x.txt

"drm" is a Linux-specific term, so shouldn't really be used as the
directory name for a binding. bindings/gpu/nvidia,tegra20-host1x.txt
would probably be just fine.

Aside from that, the bindings,
Acked-by: Stephen Warren <swar...@nvidia.com>

I don't really know anything about DRM or our display HW, so I haven't
reviewed the code at all. I certainly ack the concept of adding the
driver though! I have asked various other people at NVIDIA to give a
quick review of the code.
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Stephen Warren  
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 More options Nov 9 2012, 7:10 pm
Newsgroups: fa.linux.kernel
From: Stephen Warren <swar...@wwwdotorg.org>
Date: Sat, 10 Nov 2012 00:10:27 UTC
Local: Fri, Nov 9 2012 7:10 pm
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On 11/09/2012 06:59 AM, Thierry Reding wrote:

> This commit adds a KMS driver for the Tegra20 SoC. This includes basic
> support for host1x and the two display controllers found on the Tegra20
> SoC. Each display controller can drive a separate RGB/LVDS output.

I applied these two patches and the two arch/arm/mach-tegra patches you
posted, directly on top of next-20121109, and I see the following build
failure:

> drivers/gpu/drm/tegra/output.c: In function 'tegra_output_init':
> drivers/gpu/drm/tegra/output.c:166:9: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c:166:3: error: implicit declaration of function 'of_get_display'
> drivers/gpu/drm/tegra/output.c:167:20: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c:168:25: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c:179:13: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c:180:3: error: implicit declaration of function 'display_put'
> drivers/gpu/drm/tegra/output.c:180:21: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c:257:20: error: 'struct tegra_output' has no member named 'display'
> drivers/gpu/drm/tegra/output.c: In function 'tegra_output_exit':
> drivers/gpu/drm/tegra/output.c:272:20: error: 'struct tegra_output' has no member named 'display'

Does this depend on something not in linux-next?
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Terje Bergström  
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 More options Nov 10 2012, 1:04 pm
Newsgroups: fa.linux.kernel
From: Terje Bergström <tbergst...@nvidia.com>
Date: Sat, 10 Nov 2012 18:04:53 UTC
Local: Sat, Nov 10 2012 1:04 pm
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On 09.11.2012 23:03, Thierry Reding wrote:
> On Fri, Nov 09, 2012 at 10:26:27AM -0600, Rob Clark wrote:
>> hmm, are these values defined by the hw? They look like register
>> offsets into the DC block?
> I don't think they are defined by the hardware. From what I gather these
> can arbitrarily be assigned by software. If things actually work the way
> I think they do, then eventually these values could be allocated by the
> host1x_register_client() function and stored within the host1x_client
> structure, so that each HW block can program them into the corresponding
> register.

These are host1x sync points. Sync points are used to synchronize work
between host1x, host1x client units (like DC, 2D, EPP, etc), and CPU.
Tegra2 TRM now contains chapters for HOST1X, 2D and EPP, so it has some
more details.

The assignment of sync points is a software policy. Depending on
programming model of client unit, one or more sync points are used for
each. For example, for each DC we have one sync point assigned to
vblank, and one for each DC window. For 2D, we'd have one sync point,
and a choice of using the same of different sync point for EPP.

We could either assign sync point registers by hard coding, or assign
them dynamically one per client unit, and possibly an additional one
depending on the programming model. Sync points are a scarce resource,
so we've so far preferred to do static assignment to catch
overallocation as early as possible.

Terje
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Discussion subject changed to "drm: tegra: Add HDMI support" by Daniel Vetter
Daniel Vetter  
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 More options Nov 11 2012, 9:45 am
Newsgroups: fa.linux.kernel
From: Daniel Vetter <dan...@ffwll.ch>
Date: Sun, 11 Nov 2012 14:45:47 UTC
Local: Sun, Nov 11 2012 9:45 am
Subject: Re: [PATCH 2/2] drm: tegra: Add HDMI support

Sounds good, especially the disdinction between the infoframe creation and
packing. E.g. on intel sdvo outputs we may not put in one of the ECC bytes
(since the hw creates it), so we need our own packing code there.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Daniel Vetter  
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 More options Nov 12 2012, 4:44 am
Newsgroups: fa.linux.kernel
From: Daniel Vetter <dan...@ffwll.ch>
Date: Mon, 12 Nov 2012 09:44:02 UTC
Local: Mon, Nov 12 2012 4:44 am
Subject: Re: [PATCH 2/2] drm: tegra: Add HDMI support
On Mon, Nov 12, 2012 at 8:24 AM, Thierry Reding

<thierry.red...@avionic-design.de> wrote:
> Actually what I had in mind was a packed binary representation of
> infoframes as specified by HDMI 1.3a (I don't have access to 1.4, but I
> would think it doesn't differ in this respect) in section 5.3 and 5.3.5
> more specifically. According to the specification, the ECC bytes only
> come into play at a later stage, when data is actually transmitted on
> the TMDS link (Section 5.2.3). Tegra, nouveau and radeon also seem to be
> doing the checksumming in hardware, so I guess we don't need to compute
> the ECC bytes in software at all (for now).

> Once we have this for the AVI infoframes I guess the same concept can be
> used for audio infoframes and for vendor-specific infoframes (for HDMI
> 1.4 3D).

Iirc there's more than one checksum: The ECC field at byte 3 and the
checksum field at byte 4. All intel hw computes the ECC itself, but
some want us to store the infoframe with an empty ECC byte as
placeholder, whereas others (sdvo encoders) insert that byte
themselves, i.e. the infoframe is actually one byte shorter. In any
case, that kind of mangling can be done in the driver with easy.
-Daniel
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Discussion subject changed to "NVIDIA Tegra DRM driver" by Thierry Reding
Thierry Reding  
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 More options Nov 12 2012, 4:56 pm
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Mon, 12 Nov 2012 21:56:19 UTC
Local: Mon, Nov 12 2012 4:56 pm
Subject: [PATCH v2 0/2] NVIDIA Tegra DRM driver
This second version of this patch series addresses all the comments
received so far. Most notably it takes advantage of the debugfs helpers
provided by the DRM core. Oddly enough this actually increases the line
count, but that's because the helpers don't fit with the subdevices
approach as implemented by this driver. However some quick discussions
with Rob Clark showed that Tegra DRM is not special in this respect but
other drivers may need the same functionality. Eventually the debugfs
code could be reworked on top of helpers that are better suited at the
design of embedded, multi-device DRM drivers.

Other than that there is some removal of code that was actually supposed
to go into a later patch because it has dependencies that haven't been
merged yet and some moving around of #defines and the device tree
bindings documentation. Finally the driver now uses the DRM core's
drm_compat_ioctl() instead of a custom and unimplemented (!) version.

Thierry

Thierry Reding (2):
  drm: Add NVIDIA Tegra20 support
  drm: tegra: Add HDMI support

 .../bindings/gpu/nvidia,tegra20-host1x.txt         |  191 +++
 drivers/gpu/drm/Kconfig                            |    2 +
 drivers/gpu/drm/Makefile                           |    1 +
 drivers/gpu/drm/tegra/Kconfig                      |   23 +
 drivers/gpu/drm/tegra/Makefile                     |    7 +
 drivers/gpu/drm/tegra/dc.c                         |  846 +++++++++++++
 drivers/gpu/drm/tegra/dc.h                         |  388 ++++++
 drivers/gpu/drm/tegra/drm.c                        |  115 ++
 drivers/gpu/drm/tegra/drm.h                        |  233 ++++
 drivers/gpu/drm/tegra/fb.c                         |   56 +
 drivers/gpu/drm/tegra/hdmi.c                       | 1324 ++++++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.h                       |  575 +++++++++
 drivers/gpu/drm/tegra/host1x.c                     |  321 +++++
 drivers/gpu/drm/tegra/output.c                     |  262 ++++
 drivers/gpu/drm/tegra/rgb.c                        |  200 +++
 15 files changed, 4544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
 create mode 100644 drivers/gpu/drm/tegra/Kconfig
 create mode 100644 drivers/gpu/drm/tegra/Makefile
 create mode 100644 drivers/gpu/drm/tegra/dc.c
 create mode 100644 drivers/gpu/drm/tegra/dc.h
 create mode 100644 drivers/gpu/drm/tegra/drm.c
 create mode 100644 drivers/gpu/drm/tegra/drm.h
 create mode 100644 drivers/gpu/drm/tegra/fb.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.h
 create mode 100644 drivers/gpu/drm/tegra/host1x.c
 create mode 100644 drivers/gpu/drm/tegra/output.c
 create mode 100644 drivers/gpu/drm/tegra/rgb.c

--
1.8.0

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Discussion subject changed to "drm: tegra: Add HDMI support" by Thierry Reding
Thierry Reding  
View profile  
 More options Nov 12 2012, 4:56 pm
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Mon, 12 Nov 2012 21:56:32 UTC
Local: Mon, Nov 12 2012 4:56 pm
Subject: [PATCH v2 2/2] drm: tegra: Add HDMI support
This commit adds support for the HDMI output on the Tegra20 SoC. Only
one such output is available, but it can be driven by either of the two
display controllers.

A lot of work on this patch has been contributed by NVIDIA's Mark Zhang
<ma...@nvidia.com> and many other people at NVIDIA were very helpful in
getting the HDMI support and surrounding infrastructure to work.

Signed-off-by: Thierry Reding <thierry.red...@avionic-design.de>
---
Changes in v2:
- reuse debugfs infrastructure provided by the DRM core

 drivers/gpu/drm/tegra/Makefile |    2 +-
 drivers/gpu/drm/tegra/drm.h    |    2 +
 drivers/gpu/drm/tegra/hdmi.c   | 1324 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.h   |  575 +++++++++++++++++
 drivers/gpu/drm/tegra/host1x.c |    8 +
 5 files changed, 1910 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/tegra/hdmi.c
 create mode 100644 drivers/gpu/drm/tegra/hdmi.h

diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 624a807..80f73d1 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -2,6 +2,6 @@ ccflags-y := -Iinclude/drm
 ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG

 tegra-drm-y := drm.o fb.o dc.o host1x.o
-tegra-drm-y += output.o rgb.o
+tegra-drm-y += output.o rgb.o hdmi.o

 obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index a1a891e..c2c4d16 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -131,6 +131,7 @@ struct tegra_output_ops {

 enum tegra_output_type {
        TEGRA_OUTPUT_RGB,
+       TEGRA_OUTPUT_HDMI,
 };

 struct tegra_output {
@@ -225,6 +226,7 @@ extern int tegra_drm_fb_init(struct drm_device *drm);
 extern void tegra_drm_fb_exit(struct drm_device *drm);

 extern struct platform_driver tegra_host1x_driver;
+extern struct platform_driver tegra_hdmi_driver;
 extern struct platform_driver tegra_dc_driver;
 extern struct drm_driver tegra_drm_driver;

diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
new file mode 100644
index 0000000..61a1d14
--- /dev/null
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -0,0 +1,1324 @@
+/*
+ * Copyright (C) 2012 Avionic Design GmbH
+ * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/clk.h>
+
+#include "hdmi.h"
+#include "drm.h"
+#include "dc.h"
+
+struct tegra_hdmi {
+       struct host1x_client client;
+       struct tegra_output output;
+       struct device *dev;
+
+       struct regulator *vdd;
+       struct regulator *pll;
+
+       void __iomem *regs;
+       unsigned int irq;
+
+       struct clk *clk_parent;
+       struct clk *clk;
+
+       unsigned int audio_source;
+       unsigned int audio_freq;
+       bool stereo;
+       bool dvi;
+
+       struct drm_info_list *debugfs_files;
+       struct drm_minor *minor;
+       struct dentry *debugfs;
+};
+
+static inline struct tegra_hdmi *
+host1x_client_to_hdmi(struct host1x_client *client)
+{
+       return container_of(client, struct tegra_hdmi, client);
+}
+
+static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
+{
+       return container_of(output, struct tegra_hdmi, output);
+}
+
+#define HDMI_AUDIOCLK_FREQ 216000000
+#define HDMI_REKEY_DEFAULT 56
+
+enum {
+       AUTO = 0,
+       SPDIF,
+       HDA,
+};
+
+static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
+                                            unsigned long reg)
+{
+       return readl(hdmi->regs + (reg << 2));
+}
+
+static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
+                                    unsigned long reg)
+{
+       writel(val, hdmi->regs + (reg << 2));
+}
+
+struct tegra_hdmi_audio_config {
+       unsigned int pclk;
+       unsigned int n;
+       unsigned int cts;
+       unsigned int aval;
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
+       {  25200000, 4096,  25200, 24000 },
+       {  27000000, 4096,  27000, 24000 },
+       {  74250000, 4096,  74250, 24000 },
+       { 148500000, 4096, 148500, 24000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
+       {  25200000, 5880,  26250, 25000 },
+       {  27000000, 5880,  28125, 25000 },
+       {  74250000, 4704,  61875, 20000 },
+       { 148500000, 4704, 123750, 20000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
+       {  25200000, 6144,  25200, 24000 },
+       {  27000000, 6144,  27000, 24000 },
+       {  74250000, 6144,  74250, 24000 },
+       { 148500000, 6144, 148500, 24000 },
+       {         0,    0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
+       {  25200000, 11760,  26250, 25000 },
+       {  27000000, 11760,  28125, 25000 },
+       {  74250000,  9408,  61875, 20000 },
+       { 148500000,  9408, 123750, 20000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
+       {  25200000, 12288,  25200, 24000 },
+       {  27000000, 12288,  27000, 24000 },
+       {  74250000, 12288,  74250, 24000 },
+       { 148500000, 12288, 148500, 24000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
+       {  25200000, 23520,  26250, 25000 },
+       {  27000000, 23520,  28125, 25000 },
+       {  74250000, 18816,  61875, 20000 },
+       { 148500000, 18816, 123750, 20000 },
+       {         0,     0,      0,     0 },
+};
+
+static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
+       {  25200000, 24576,  25200, 24000 },
+       {  27000000, 24576,  27000, 24000 },
+       {  74250000, 24576,  74250, 24000 },
+       { 148500000, 24576, 148500, 24000 },
+       {         0,     0,      0,     0 },
+};
+
+struct tmds_config {
+       unsigned int pclk;
+       u32 pll0;
+       u32 pll1;
+       u32 pe_current;
+       u32 drive_current;
+};
+
+static const struct tmds_config tegra2_tmds_config[] = {
+       { /* 480p modes */
+               .pclk = 27000000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+               .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_0_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       }, { /* 720p modes */
+               .pclk = 74250000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_6_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       }, { /* 1080p modes */
+               .pclk = UINT_MAX,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(3),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_6_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_6_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+       },
+};
+
+static const struct tmds_config tegra3_tmds_config[] = {
+       { /* 480p modes */
+               .pclk = 27000000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+               .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_0_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_0_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+       }, { /* 720p modes */
+               .pclk = 74250000,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_5_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+       }, { /* 1080p modes */
+               .pclk = UINT_MAX,
+               .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+                       SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
+                       SOR_PLL_TX_REG_LOAD(0),
+               .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+               .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT1(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT2(PE_CURRENT_5_0_mA) |
+                       PE_CURRENT3(PE_CURRENT_5_0_mA),
+               .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+                       DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+              
...

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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Thierry Reding
Thierry Reding  
View profile  
 More options Nov 12 2012, 4:56 pm
Newsgroups: fa.linux.kernel
From: Thierry Reding <thierry.red...@avionic-design.de>
Date: Mon, 12 Nov 2012 21:56:47 UTC
Local: Mon, Nov 12 2012 4:56 pm
Subject: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.

Signed-off-by: Thierry Reding <thierry.red...@avionic-design.de>
---
Changes in v2:
- drop Linux-specific drm subdirectory for DT bindings documentation
- remove display helper leftovers that belong in a later patch
- reuse debugfs infrastructure provided by the DRM core
- move vblank syncpoint defines to dc.h
- use drm_compat_ioctl()

 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 191 +++++
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/tegra/Kconfig                      |  23 +
 drivers/gpu/drm/tegra/Makefile                     |   7 +
 drivers/gpu/drm/tegra/dc.c                         | 846 +++++++++++++++++++++
 drivers/gpu/drm/tegra/dc.h                         | 388 ++++++++++
 drivers/gpu/drm/tegra/drm.c                        | 115 +++
 drivers/gpu/drm/tegra/drm.h                        | 231 ++++++
 drivers/gpu/drm/tegra/fb.c                         |  56 ++
 drivers/gpu/drm/tegra/host1x.c                     | 313 ++++++++
 drivers/gpu/drm/tegra/output.c                     | 262 +++++++
 drivers/gpu/drm/tegra/rgb.c                        | 200 +++++
 13 files changed, 2635 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
 create mode 100644 drivers/gpu/drm/tegra/Kconfig
 create mode 100644 drivers/gpu/drm/tegra/Makefile
 create mode 100644 drivers/gpu/drm/tegra/dc.c
 create mode 100644 drivers/gpu/drm/tegra/dc.h
 create mode 100644 drivers/gpu/drm/tegra/drm.c
 create mode 100644 drivers/gpu/drm/tegra/drm.h
 create mode 100644 drivers/gpu/drm/tegra/fb.c
 create mode 100644 drivers/gpu/drm/tegra/host1x.c
 create mode 100644 drivers/gpu/drm/tegra/output.c
 create mode 100644 drivers/gpu/drm/tegra/rgb.c

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
new file mode 100644
index 0000000..b4fa934
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -0,0 +1,191 @@
+NVIDIA Tegra host1x
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-host1x"
+- reg: Physical base address and length of the controller's registers.
+- interrupts: The interrupt outputs from the controller.
+- #address-cells: The number of cells used to represent physical base addresses
+  in the host1x address space. Should be 1.
+- #size-cells: The number of cells used to represent the size of an address
+  range in the host1x address space. Should be 1.
+- ranges: The mapping of the host1x address space to the CPU address space.
+
+The host1x top-level node defines a number of children, each representing one
+of the following host1x client modules:
+
+- mpe: video encoder
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-mpe"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- vi: video input
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-vi"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- epp: encoder pre-processor
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-epp"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- isp: image signal processor
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-isp"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- gr2d: 2D graphics engine
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-gr2d"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- gr3d: 3D graphics engine
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-gr3d"
+  - reg: Physical base address and length of the controller's registers.
+
+- dc: display controller
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-dc"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+  Each display controller node has a child node, named "rgb", that represents
+  the RGB output associated with the controller. It can take the following
+  optional properties:
+  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+  - nvidia,edid: supplies a binary EDID blob
+
+- hdmi: High Definition Multimedia Interface
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-hdmi"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+  - vdd-supply: regulator for supply voltage
+  - pll-supply: regulator for PLL
+
+  Optional properties:
+  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+  - nvidia,edid: supplies a binary EDID blob
+
+- tvo: TV encoder output
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-tvo"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+
+- dsi: display serial interface
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-dsi"
+  - reg: Physical base address and length of the controller's registers.
+
+Example:
+
+/ {
+       ...
+
+       host1x {
+               compatible = "nvidia,tegra20-host1x", "simple-bus";
+               reg = <0x50000000 0x00024000>;
+               interrupts = <0 65 0x04   /* mpcore syncpt */
+                             0 67 0x04>; /* mpcore general */
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               ranges = <0x54000000 0x54000000 0x04000000>;
+
+               mpe {
+                       compatible = "nvidia,tegra20-mpe";
+                       reg = <0x54040000 0x00040000>;
+                       interrupts = <0 68 0x04>;
+               };
+
+               vi {
+                       compatible = "nvidia,tegra20-vi";
+                       reg = <0x54080000 0x00040000>;
+                       interrupts = <0 69 0x04>;
+               };
+
+               epp {
+                       compatible = "nvidia,tegra20-epp";
+                       reg = <0x540c0000 0x00040000>;
+                       interrupts = <0 70 0x04>;
+               };
+
+               isp {
+                       compatible = "nvidia,tegra20-isp";
+                       reg = <0x54100000 0x00040000>;
+                       interrupts = <0 71 0x04>;
+               };
+
+               gr2d {
+                       compatible = "nvidia,tegra20-gr2d";
+                       reg = <0x54140000 0x00040000>;
+                       interrupts = <0 72 0x04>;
+               };
+
+               gr3d {
+                       compatible = "nvidia,tegra20-gr3d";
+                       reg = <0x54180000 0x00040000>;
+               };
+
+               dc@54200000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54200000 0x00040000>;
+                       interrupts = <0 73 0x04>;
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               dc@54240000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54240000 0x00040000>;
+                       interrupts = <0 74 0x04>;
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               hdmi {
+                       compatible = "nvidia,tegra20-hdmi";
+                       reg = <0x54280000 0x00040000>;
+                       interrupts = <0 75 0x04>;
+                       status = "disabled";
+               };
+
+               tvo {
+                       compatible = "nvidia,tegra20-tvo";
+                       reg = <0x542c0000 0x00040000>;
+                       interrupts = <0 76 0x04>;
+                       status = "disabled";
+               };
+
+               dsi {
+                       compatible = "nvidia,tegra20-dsi";
+                       reg = <0x54300000 0x00040000>;
+                       status = "disabled";
+               };
+       };
+
+       ...
+};
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 18321b68b..983201b 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -210,3 +210,5 @@ source "drivers/gpu/drm/mgag200/Kconfig"
 source "drivers/gpu/drm/cirrus/Kconfig"

 source "drivers/gpu/drm/shmobile/Kconfig"
+
+source "drivers/gpu/drm/tegra/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2ff5cef..0bfda06 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -48,4 +48,5 @@ obj-$(CONFIG_DRM_GMA500) += gma500/
 obj-$(CONFIG_DRM_UDL) += udl/
 obj-$(CONFIG_DRM_AST) += ast/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
+obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-y                  += i2c/
diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
new file mode 100644
index 0000000..be1daf7
--- /dev/null
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -0,0 +1,23 @@
+config DRM_TEGRA
+       tristate "NVIDIA Tegra DRM"
+       depends on DRM && OF && ARCH_TEGRA
+       select DRM_KMS_HELPER
+       select DRM_GEM_CMA_HELPER
+       select DRM_KMS_CMA_HELPER
+       select FB_CFB_FILLRECT
+       select FB_CFB_COPYAREA
+       select FB_CFB_IMAGEBLIT
+       help
+         Choose this option if you have an NVIDIA Tegra SoC.
+
+         To compile this driver as a module, choose M here: the module
+         will be called tegra-drm.
+
+if DRM_TEGRA
+
+config DRM_TEGRA_DEBUG
+       bool "NVIDIA Tegra DRM debug support"
+       help
+         Say yes here to enable debugging support.
+
+endif
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
new file mode 100644
index 0000000..624a807
--- /dev/null
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
+
+tegra-drm-y := drm.o fb.o dc.o host1x.o
+tegra-drm-y += output.o rgb.o
+
+obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
new file mode 100644
index 0000000..3f759a4
--- /dev/null
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -0,0 +1,846 @@
+/*
+ * Copyright (C) 2012 Avionic Design GmbH
+ * Copyright (C) ...

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Discussion subject changed to "NVIDIA Tegra DRM driver" by Stephen Warren
Stephen Warren  
View profile  
 More options Nov 12 2012, 7:17 pm
Newsgroups: fa.linux.kernel
From: Stephen Warren <swar...@wwwdotorg.org>
Date: Tue, 13 Nov 2012 00:17:28 UTC
Local: Mon, Nov 12 2012 7:17 pm
Subject: Re: [PATCH v2 0/2] NVIDIA Tegra DRM driver
On 11/12/2012 02:55 PM, Thierry Reding wrote:

> This second version of this patch series addresses all the comments
> received so far. Most notably it takes advantage of the debugfs helpers
> provided by the DRM core. Oddly enough this actually increases the line
> count, but that's because the helpers don't fit with the subdevices
> approach as implemented by this driver. However some quick discussions
> with Rob Clark showed that Tegra DRM is not special in this respect but
> other drivers may need the same functionality. Eventually the debugfs
> code could be reworked on top of helpers that are better suited at the
> design of embedded, multi-device DRM drivers.

> Other than that there is some removal of code that was actually supposed
> to go into a later patch because it has dependencies that haven't been
> merged yet and some moving around of #defines and the device tree
> bindings documentation. Finally the driver now uses the DRM core's
> drm_compat_ioctl() instead of a custom and unimplemented (!) version.

The series,

Tested-by: Stephen Warren <swar...@nvidia.com>

(on the Harmony board's HDMI output; I'll test other boards/outputs later).
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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Mark Zhang
Mark Zhang  
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 More options Nov 13 2012, 2:16 am
Newsgroups: fa.linux.kernel
From: Mark Zhang <ma...@nvidia.com>
Date: Tue, 13 Nov 2012 07:16:47 UTC
Local: Tues, Nov 13 2012 2:16 am
Subject: Re: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
On 11/13/2012 05:55 AM, Thierry Reding wrote:

Just for curious, according to my testing, why the "CONFIG_CMA" is not
enabled while DRM_GEM_CMA_HELPER & DRM_KMS_CMA_HELPER are enabled here?

If you don't want add Tegra 3 support in this patch set, remove
{ .compatible = "nvidia,tegra30-dc", } here.

...

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Discussion subject changed to "drm: tegra: Add HDMI support" by Mark Zhang
Mark Zhang  
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 More options Nov 13 2012, 2:28 am
Newsgroups: fa.linux.kernel
From: Mark Zhang <ma...@nvidia.com>
Date: Tue, 13 Nov 2012 07:28:20 UTC
Local: Tues, Nov 13 2012 2:28 am
Subject: Re: [PATCH v2 2/2] drm: tegra: Add HDMI support
The patch is OK. Acknowledged. Thanks.

Mark
On 11/13/2012 05:55 AM, Thierry Reding wrote:

...

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Discussion subject changed to "drm: Add NVIDIA Tegra20 support" by Terje Bergström
Terje Bergström  
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 More options Nov 13 2012, 2:56 am
Newsgroups: fa.linux.kernel
From: Terje Bergström <tbergst...@nvidia.com>
Date: Tue, 13 Nov 2012 07:56:58 UTC
Local: Tues, Nov 13 2012 2:56 am
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On 09.11.2012 15:59, Thierry Reding wrote:

> This commit adds a KMS driver for the Tegra20 SoC. This includes basic
> support for host1x and the two display controllers found on the Tegra20
> SoC. Each display controller can drive a separate RGB/LVDS output.

Thanks Thierry for the hard work. I noticed the same thing Stephen
noticed earlier - I couldn't compile the driver.

Other than that, there were a couple of differences to the tree we've
worked with and tested earlier: Tegra30 support was dropped and as a
consequence so was IOMMU support.

I'm perfectly fine with leaving out IOMMU support, because we had some
problems with that and dma-buf. We were getting a bit worried about how
to implement mapping and re-mapping dma-buf's without causing duplicate
IOMMU mappings.

Best regards,
Terje
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Terje Bergström  
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 More options Nov 13 2012, 3:13 am
Newsgroups: fa.linux.kernel
From: Terje Bergström <tbergst...@nvidia.com>
Date: Tue, 13 Nov 2012 08:13:28 UTC
Local: Tues, Nov 13 2012 3:13 am
Subject: Re: [PATCH 1/2] drm: Add NVIDIA Tegra20 support
On 13.11.2012 10:03, Thierry Reding wrote:

> That should be fixed with v2 I posted a few hours ago.

That's true.

> Yes, Tegra30 support will follow in a separate patch. As for IOMMU
> support it should eventually be made completely transparent, but I'm not
> opposed to adding a patch with explicit IOMMU support back in if it
> turns out that it can't be done transparently.

The trouble with this is that the generic case demands that we support
each device having a separate address space. But, on Tegra30 SMMU has
only four address spaces, so in Tegra30 case we actually end up using
the same address space for multiple devices.

Second problem is trying to avoid double mapping. With 2D acceleration,
we need support for allocating buffers, and mapping them to DC, host1x
and 2D. DMA Mapping API has a problem in that it doesn't allow just
allocating - it forces mapping the buffer to a device at the same time.
So, when 2D submit contains a reference to a dma-buf, the buffer has
already been mapped to some device, but we don't have a good way of
detecting that. We end up mapping it again, which is a performance
killer and possibly a coherence problem.

Fortunately this is all related to 2D acceleration, so we can defer both
of these problems for now.

Best regards,
Terje

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Mark Zhang  
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 More options Nov 13 2012, 3:49 am
Newsgroups: fa.linux.kernel
From: Mark Zhang <ma...@nvidia.com>
Date: Tue, 13 Nov 2012 08:49:51 UTC
Local: Tues, Nov 13 2012 3:49 am
Subject: Re: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
On 11/13/2012 03:48 PM, Thierry Reding wrote:

Okay. But I think it's better to turn on CMA defaultly. During my
testing, it's hard to allocate more 2MB without CMA...

My opinion is, after registration is completed, host1x_drm_client is
useless, host1x_client is enough for follow-up operations.
I still don't get how this is related with building the driver into the
kernel or as a kernel module, so if something I misunderstood, please
let me know it. Thanks.

All right, this is just coding style problem and I think your words make
sense as well.

I just feel that all dc related works should be handled in crtc while
not in output. Anyway, this is not a big deal and I think the current
implementation also makes sense.

> Thierry

> * Unknown Key
> * 0x7F3EB3A1

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Terje Bergström  
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 More options Nov 13 2012, 4:43 am
Newsgroups: fa.linux.kernel
From: Terje Bergström <tbergst...@nvidia.com>
Date: Tue, 13 Nov 2012 09:43:04 UTC
Local: Tues, Nov 13 2012 4:43 am
Subject: Re: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
On 12.11.2012 23:55, Thierry Reding wrote:

> This commit adds a KMS driver for the Tegra20 SoC. This includes basic
> support for host1x and the two display controllers found on the Tegra20
> SoC. Each display controller can drive a separate RGB/LVDS output.

I have tested this with further patches to enable display on my ventana
board. My only problem is that we don't force CMA on, but we can add
that later.

Acked-by: Terje Bergstrom <tbergst...@nvidia.com>

Best regards,
Terje
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Mark Zhang  
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 More options Nov 13 2012, 4:49 am
Newsgroups: fa.linux.kernel
From: Mark Zhang <ma...@nvidia.com>
Date: Tue, 13 Nov 2012 09:49:55 UTC
Local: Tues, Nov 13 2012 4:49 am
Subject: Re: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
On 11/13/2012 05:37 PM, Thierry Reding wrote:

Yes. We don't need to touch CMA in our Kconfig. In my opinion, right now
we're relying on the DRM_GEM_CMA_HELPER which should turn on CMA when
it's been selected.

Okay. I recall I did some changes on this part about 3 month ago in a
patch named "drm: Add T30 support - host1x". So maybe you can know what
I mean by reading that patch.

> Thierry

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> * 0x7F3EB3A1

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Mark Zhang  
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 More options Nov 13 2012, 4:58 am
Newsgroups: fa.linux.kernel
From: Mark Zhang <ma...@nvidia.com>
Date: Tue, 13 Nov 2012 09:58:19 UTC
Local: Tues, Nov 13 2012 4:58 am
Subject: Re: [PATCH v2 1/2] drm: Add NVIDIA Tegra20 support
On 11/13/2012 05:54 PM, Thierry Reding wrote:

Agree.

Okay. I'll take a look at this part as well when I'm free.

> Thierry

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