[erlang-questions] Erlang on Tilera

[Olivier BOUDEVILLE]

Hello list,

After having seen Kenneth Lundin's post about the Erlang SMP VM running on
a 64 core Tilera and the README files of R13A and R13B01, we could be
interested in giving these architectures a try.

Would it be possible to have more information regarding the actual
hardware that was tested with Erlang (processor: TilePro64?, card:
TileExpress/TileEncore/other?), the procedure that you followed (ex: to
cross-compile an Erlang VM, to select the number of nodes being used,
etc.) and your overall feeling about this architecture?

Thanks in advance for any information,
Best regards,

Olivier Boudeville.
---------------------------
Olivier Boudeville

EDF R&D : 1, avenue du Général de Gaulle, 92140 Clamart, France
Département SINETICS, groupe ASICS (I2A), bureau B-226
Office : +33 1 47 65 59 58 / Mobile : +33 6 16 83 37 22 / Fax : +33 1 47
65 27 13

[Björn-Egil Dahlberg]

Hi Olivier,

The card we at Erlang/OTP worked with was the TileExpress-64 card.
We had two different methods of building Erlang for Tilera. Tilera Corp
did a native build on their cards when they did testing and we did a
cross-compilation. Both methods works good.

Cross compiling has several steps. For example, a host VM is built to
compile beam-code and then a cross-compiled VM is built for the tile-cpu
target.

For a user compiling otp-source for a Tilera card there is a couple of
steps to go through. The most significant is setting up the environment
correctly, this is done with,

./otp_build env_cross $ERL_TOP/xcomp/erl-xcomp-TileraMDE2.0-tilepro.conf

and then autoconf, configure, boot, release in the usual manner using
the otp_build script.

We were very interested to work with the Tilera-cards because of its
manycore environment and this was good opportunity for us to test our
runtime-system on a manycore platform and to evaluate Erlang/OTP
performance. Our main concerns was of course scalability and Erlang
IPC-communication with many schedulers and we designed our tests with
this in mind. We were for instance concerned about the obvious single
run-queue problem with many schedulers and wanted to measure its impact.
We also wanted to test solution and ways to combat this and other
potential problems. We had, and still have, a very fruitful exchange
with Tilera Corp. on improvements for the runtime-system both in general
and specifically targeted to the Tilera cards.

We were only interested in testing a single node utilizing all cores and
evaluating performance with increasing number of schedulers for
different scenarios. We did not evaluate the card, we only evaluated
Erlang runtime-system performance. For information on Tilera-card
performance I recommend contacting Tilera Corp. directly.

Erlang performance on manycore-platforms is correlated to how good the
application is designed and this is also true for scalability. It is
however easier to make an application more scalable in Erlang using our
design-pattern and our mindset with many processes.

Regards,
Björn-Egil
Erlang/OTP, Ericsson AB

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[Olivier BOUDEVILLE]

Hi Björn-Egil,

Thanks a lot for your answer. As I understand, we could gain access to a
compatible Erlang VM without needing to purchase any too expensive Tilera
SDK? That looks promising!

If the decision to perform some testing and benchmarks (no sooner than the
end of this year) is acknowledged internally, I will have to consider
whether we should stick to the same card and processor as the ones you
tested, or if upgrading/updating them a bit should be still safe regarding
the Erlang support (processor: TILE64 -> TILEPro64; card: TILExpress-54 ->
TILEncorePro-64); would you have any recommendation? I hope Tilera will be
able to give some advice too.

Finally, would a HIPE native (cross-)compilation of modules, targeting a
tile, make any sense/would be possible/could lead to largely increased
performances?

Thanks in advance for any information,
Best regards,

Olivier Boudeville.
---------------------------
Olivier Boudeville

EDF R&D : 1, avenue du Général de Gaulle, 92140 Clamart, France
Département SINETICS, groupe ASICS (I2A), bureau B-226
Office : +33 1 47 65 59 58 / Mobile : +33 6 16 83 37 22 / Fax : +33 1 47
65 27 13

eg...@erix.ericsson.se
22/06/2009 18:09

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olivier.b...@edf.fr
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Re: [erlang-questions] Erlang on Tilera

[Mikael Pettersson]

Olivier BOUDEVILLE writes:
> Finally, would a HIPE native (cross-)compilation of modules, targeting a
> tile, make any sense/would be possible/could lead to largely increased
> performances?

At the moment no, because HiPE cannot generate MIPS object code.
(And generating MIPS code will be a challenge due to its lack of
condition codes, which affects Erlang arithmetic.)

If anyone wants MIPS support in HiPE, consider donating some HW.

[Raoul Duke]

> If anyone wants MIPS support in HiPE, consider donating some HW.

http://en.wikipedia.org/wiki/MIPS_architecture#Simulators

? :-)