On implementing PDK-s rules and tech description for Electric

[Alexandre Rusev]

One of possible approaches to implement freepdk (and other PDK-s techns)

for electric may be converting various technology descriptions from Cadence format, using any available PDK.

The generic PDK from Cadence is one of possible variants.

https://perso.telecom-paristech.fr/mathieu/ICS904_TP_LAYOUT/html/_static/doc/gpdk045_drc.pdf

We also can take look at simpler PDK-s likes freely available organic process PDK

http://opdk.umn.edu/tutorial2.html

Helpfull docs on Cadence DRC and tech format descriptions I found

in Utah>

http://www.cs.utah.edu/~rfonnesb/ee6961/docs/

We also need to look at technology layers manual (with usefull figures in it;) ) to edit electric technology file.

Looking for information in google I encounted a nice piece of educational CAD which calls MicroWind

http://www.microwind.net/

This is eduactional only and tool, yet it demonstrates main features of various submicrone technologies, rule files a the text files and are freely available.

https://github.com/shmmy/vlsi/tree/master/vlsi_2011/MW3.1.7/MW3.1.7/rules

Besides coding correct DRC rules we need to make ensure that our electric tech description exports the GDS layers needed to the target fab to create working layout.

For this purpose we need to generate some reference layouts with

cadence tools (as long as we are porting cadence oriented pdk-s to electric)

We also need to exchange with EDIF netlist format between electric and cadence/calibre and compare LVS results of both cads.

We also need to extract SPICE models for ELDO or Spectre model files which are typically provided with cadence oriented PDK-s.

Generally may be we need to start with simpler point - just to look at

DRC description examples for Cadence, Microwind, TaannerEDA and code technology layers for Electric...

I am working on that last (simplified) approach...

adding their layers

https://www.eda.ncsu.edu/wiki/FreePDK45:Layers

and implementing their rules

https://www.eda.ncsu.edu/wiki/FreePDK45:Contents

may be NOT a "rocket science" itself, but it looks like that I have now full access to all FreePDK45 resources, not being an academic user.

We need detail information on sheet resistance, parasitic capacitance and so on.

It still not clear which fab will produce chips designed for this PDK :(

Support of fab-s models in NGSpice is aso an issue, at the moment I do not know how to simulate their "new fasioned" BSIM model with LEVEL 53

[Travis Ayres]

I'll bet anything that all Cadence files specify in their license that you are not to use them with other tools, not to use them for the purpose of implementing them in other tools, and probably required by license not to think of other tools while you're using them.

I'm not a lawyer, but I sincerely doubt you could do this in a legally kosher way if you start from a Cadence file. 

"I can find the Cadence files online" isn't a license to use them how you want.

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[Mircea Stan]

You cannot fabricate a layout using FreePDK, so getting Electric to work with that PDK wouldn't be that useful. The only relatively straightforward approach for getting a chip fabricated using Electric nowadays seems to be in TSMC 250nm, available through MOSIS MPW and still apparently accepting SCMOS DEEP lambda design rules which are compatible with Electric.

[Joselito Morallo]

Hi to All!

I am interested to this thread due to my previous experience in Layout Design of Integrated Circuit. 

I believed each tool has its own layout design database file and converting it to gds file can perform drc and lvs. the challenge is the rule checker from the technology provider(fab process).

if we can figure out Standard Analog Cells for IC designers in 90nm, 45nm and down is very good to us using electric. Any derivation of circuit we can perform by simulating through electric the PMOS amd NMOS. Have soneone tried this in their design house?

Best Regards, 

Joselito