csarch Google Group

simulator for vector processor

2009-09-25T06:23:47Z

Hi,
I searched but found no simulator for vector processors. For example
virtutech has a lot of targets and platforms but nothing is available
for vector platforms such as cray, NEC SX and ...

Anybody can help?

simulators that could run mpi benchmarks.

2009-07-10T03:27:58Z

hi, all,

do you know any simulators that could run MPI benchmarks ? i'm doing
some architecture research, it's very important for me...

i've tried m5, but it's tough and hard to use...

do you have any good ideas, hints or tips ?

Re: [csarch] Re: 如果要<>3rd~,我有.

2008-09-15T18:10:18Z

Another conceptual level question regarding to the multi-core processor.
Obviously the multiprocessor core will need much higher bandwidh than the
conventional single one.
E.g. Sun T1 got 25.6GB (1.2 GHZ) nd Pentium got 6.4 GB(3.2 GHZ).
I am just wondering whether the power gain get from the processor will be

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Re: [csarch] Re: 如果要<>3rd~,我有.

2008-08-29T17:01:56Z

RAS = Return Address Stack. It is used to predict the targets of
return instructions.
A SMT processor normally fetches instructions in a round-robin way
from all ready threads. Those N threads are typically different. (Your
assumption is not true in most cases). So the wrongly fetched
instructions are only 1/N of that in the single thread case.

Re: [csarch] Re: 如果要<>3rd~,我有.

2008-08-27T22:28:43Z

Thanks Navy Ant. Two further thoughts & questions:
a. What do you mean by RAS,
b. For the second fact the SMT got less wrong path fetched,I am not sure
how I understand it correctly. But I can make a stupid example. If I got 8
thread(e.g. assume it exactly the same), it will fetch 8N wrong
instructions. However, in a 8-thread processor, if i ignore the pipelien

Re: [csarch] Re: 如果要<>3rd~,我有.

2008-08-26T21:03:18Z

From the context, a shared branch predictor is assumed. Power 5 uses a
shared one (only RAS is separate), for example. I would assume
normally a SMT processor uses shared predictor.
2008/8/26 yao gang <nobond...@gmail.com>:

Re: [csarch] 如果要<>3rd~,我有.

2008-08-26T17:37:59Z

I found the following paraph is hard to understand.
*The following results are seen from a simulation study of five
floating-point benchmarks and two integer benchmarks from the SPEC92 suite.
The branch misprediction rate nearly doubles from 5% to 9.1% going from 1
thread to 8 threads in an SMT processor. However, the wrong-path

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2008-03-28T10:06:34Z

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2008-03-19T13:33:59Z

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2008-01-06T09:35:27Z

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Re: Having problem with GEMS

2007-07-23T16:27:48Z

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On 6月21日, 下午1时56分, "Intekhab Sadekin" <blackjack002...@gmail.com>
wrote: