Internal channel communication query.

[Gavin Crate]

I’m in the process of adding realistic processor instruction cycle
timing to the Transputer Emulator (http://sites.google.com/site/
transputeremulator/) and have a query concerning internal channel
communications.

According to the T414 datasheet an ‘in’ or ‘out’ instruction will take
2w + 19 processor cycles (where w is number of words in the message).

So if a process (called P) is executing an ‘out’ instruction using an
internal channel, and a process (called Q) is executing an ‘in’
instruction using the same internal channel, do both processes
instructions 2w + 19 processor cycles to complete?

Obviously, there is a memory transfer to move the data from the
destination specified by the ‘in’ instruction, which I can see is 2w,
but why both instructions 2w?

Hence is it the actual case that ‘out’ instruction takes 19 processor
cycles, and the ‘in’ instruction takes 2w + 19 processor cycles?

Thoughts

Gavin

[Gavin Crate]

> Hence is it the actual case that ‘out’ instruction takes 19 processor
> cycles, and the ‘in’ instruction takes 2w + 19 processor cycles?

Or that the ‘out’ instruction takes 2w + 19 processor cycles, and the
‘in’ instruction takes 19 processor cycles, if the 'in' instruction
was executed and descheduled first?

[Mike B.]

Look into the TRANSPUTER INSTRUCTION SET - A compiler writer's guide
on Page 117:

2w+18 input message - communication procedes
20 input message - communication waits

the same for output message.

So the first ready process gets 20 cycles and the second 2w+18 cycles
regardless which is in or out.

w ... the number of words, plus non word aligned part words, in a
message

and remember:

The timings assume all memory access is to on chip RAM.
The Code for out is #0B and not #07 (which is wrongly printed in my
book).

-Mike