Odd high priority process interrupting behaviour.
Gavin...@ultracontrols.aero
Below are two debugging traces from the T414 emulator initially
written by Julian Highfield. I am struggling to get the high priority
interrupt mechanism working.
The first extract 1 shows the standard execution and debugging output
(with DEBUG on) for the OC command, with the high priority
interrupting disabled (i.e. high priority tasks are disabled from
interrupting low priority tasks.
The second extract 2 shows the standard execution and debugging output
(with DEBUG on) for the OC command, but with the high priority allowed
to interrupt low priority processes switched on (i.e. after completion
of the current low priority instruction).
To view these correctly you will need to copy and paste into a
suitable text viewer/editor. These are some notes which I have added
at the end of each execution.
Extract 1
IPtr=8004C442, Instruction=D4, OReg= 4, AReg=80000000,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C443, Instruction=10, OReg= 0, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C444, Instruction=D1, OReg= 1, AReg=80000090,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C445, Instruction=48, OReg= 8, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C446, Instruction=21, OReg= 1, AReg= 8,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C447, Instruction=FB, OReg= 1B, AReg= 8,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C448, Instruction=D2, OReg= 2, AReg=8004C450,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C449, Instruction=13, OReg= 3, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44A, Instruction=23, OReg= 3, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44B, Instruction=F9, OReg= 39, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425 -- runp
(added to hi pri queue)
IPtr=8004C44C, Instruction=10, OReg= 0, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44D, Instruction=14, OReg= 4, AReg=80000090,
BReg=8000009C, CReg=80000075, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44E, Instruction=41, OReg= 1, AReg=800000A0,
BReg=80000090, CReg=8000009C, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44F, Instruction=FB, OReg= B, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=80000090, WPtr[0]= 563F425 -- out
(low pri task descheduled)
Out. Channel 800000A0, length 1, from memory at 80000090
ptr = 8000009C. FPtrReg0 (Hi) = 8000009C, FPtrReg1 (Lo) = 80000000.
IPtr=8004C450, Instruction=24, OReg= 4, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=8000009C, WPtr[0]=6266632E --
pfix (hi pri task run)
IPtr=8004C451, Instruction=F3, OReg= 43, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=8000009C, WPtr[0]=6266632E -- alt
alt: (W-3)=Enabling_p
IPtr=8004C452, Instruction=11, OReg= 1, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=8000009C, WPtr[0]=6266632E -- ldlp
IPtr=8004C453, Instruction=41, OReg= 1, AReg=800000A0,
BReg= 1, CReg=800000A0, WPtr=8000009C, WPtr[0]=6266632E -- ldc
IPtr=8004C454, Instruction=24, OReg= 4, AReg= 1,
BReg=800000A0, CReg= 1, WPtr=8000009C, WPtr[0]=6266632E -- pfix
IPtr=8004C455, Instruction=F8, OReg= 48, AReg= 1,
BReg=800000A0, CReg= 1, WPtr=8000009C, WPtr[0]=6266632E -- enbc
enbc(1): Channel 800000A0
enbc(2): Waiting internal channel: (W-3)=Ready_p
IPtr=8004C456, Instruction=24, OReg= 4, AReg= 1,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=6266632E -- pfix
IPtr=8004C457, Instruction=F4, OReg= 44, AReg= 1,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=6266632E --
altwt
altwt(1): (W)=NoneSelected_o
altwt(2): (W-3) is 80000003
IPtr=8004C458, Instruction=60, OReg= 0, AReg= 1,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=FFFFFFFF -- nfix
IPtr=8004C459, Instruction=7E, OReg=FFFFFFFE, AReg= 1,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=FFFFFFFF -- ldl
IPtr=8004C45A, Instruction=23, OReg= 3, AReg=80000090,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=FFFFFFFF -- pfix
IPtr=8004C45B, Instruction=FC, OReg= 3C, AReg=80000090,
BReg= 1, CReg= 1, WPtr=8000009C, WPtr[0]=FFFFFFFF -- gajw
IPtr=8004C45C, Instruction=21, OReg= 1, AReg=8000009C,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=80000003 --
pfix (back to WPtr=80000090 but hi pri?)
IPtr=8004C45D, Instruction=7C, OReg= 1C, AReg=8000009C,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=80000003 -- ldl
IPtr=8004C45E, Instruction=21, OReg= 1, AReg=80000128,
BReg=8000009C, CReg= 1, WPtr=80000090, WPtr[0]=80000003 -- pfix
IPtr=8004C45F, Instruction=7F, OReg= 1F, AReg=80000128,
BReg=8000009C, CReg= 1, WPtr=80000090, WPtr[0]=80000003 -- ldl
IPtr=8004C460, Instruction=33, OReg= 3, AReg=8004C1E8,
BReg=80000128, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003 -- ldnl
IPtr=8004C461, Instruction=F2, OReg= 2, AReg= 0,
BReg=80000128, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C462, Instruction=21, OReg= 1, AReg=80000128,
BReg=8000009C, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C463, Instruction=7F, OReg= 1F, AReg=80000128,
BReg=8000009C, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C464, Instruction=E3, OReg= 3, AReg=8004C1E8,
BReg=80000128, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C465, Instruction=21, OReg= 1, AReg=8000009C,
BReg=80000128, CReg=8000009C, WPtr=80000090, WPtr[0]=80000003
Extract 2
IPtr=8004C442, Instruction=D4, OReg= 4, AReg=80000000,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C443, Instruction=10, OReg= 0, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C444, Instruction=D1, OReg= 1, AReg=80000090,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C445, Instruction=48, OReg= 8, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C446, Instruction=21, OReg= 1, AReg= 8,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C447, Instruction=FB, OReg= 1B, AReg= 8,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C448, Instruction=D2, OReg= 2, AReg=8004C450,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C449, Instruction=13, OReg= 3, AReg=80000075,
BReg= 0, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44A, Instruction=23, OReg= 3, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425
IPtr=8004C44B, Instruction=F9, OReg= 39, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]= 563F425 -- runp
(hi pri task)
Interrupting a LoPriority process.
IPtr=8004C450, Instruction=24, OReg= 4, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=8000009C, WPtr[0]=6266632E -- hi
pri task run (interrupt)
IPtr=8004C451, Instruction=F3, OReg= 43, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=8000009C, WPtr[0]=6266632E
alt: (W-3)=Enabling_p
IPtr=8004C452, Instruction=11, OReg= 1, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=8000009C, WPtr[0]=6266632E
IPtr=8004C453, Instruction=41, OReg= 1, AReg=800000A0,
BReg=8000009C, CReg=80000075, WPtr=8000009C, WPtr[0]=6266632E
IPtr=8004C454, Instruction=24, OReg= 4, AReg= 1,
BReg=800000A0, CReg=8000009C, WPtr=8000009C, WPtr[0]=6266632E
IPtr=8004C455, Instruction=F8, OReg= 48, AReg= 1,
BReg=800000A0, CReg=8000009C, WPtr=8000009C, WPtr[0]=6266632E
enbc(1): Channel 800000A0
enbc(2): Link or non-waiting channel.
IPtr=8004C456, Instruction=24, OReg= 4, AReg= 1,
BReg=8000009C, CReg=8000009C, WPtr=8000009C, WPtr[0]=6266632E
IPtr=8004C457, Instruction=F4, OReg= 44, AReg= 1,
BReg=8000009C, CReg=8000009C, WPtr=8000009C, WPtr[0]=6266632E
altwt(1): (W)=NoneSelected_o
altwt(2): (W-3) is 80000001
altwt(3): (W-3)=Waiting_p
Returning to interrupted LoPriority process.
IPtr=8004C44C, Instruction=10, OReg= 0, AReg=8000009C,
BReg=80000075, CReg= 0, WPtr=80000090, WPtr[0]=80000002
IPtr=8004C44D, Instruction=14, OReg= 4, AReg=80000090,
BReg=8000009C, CReg=80000075, WPtr=80000090, WPtr[0]=80000002
IPtr=8004C44E, Instruction=41, OReg= 1, AReg=800000A0,
BReg=80000090, CReg=8000009C, WPtr=80000090, WPtr[0]=80000002
IPtr=8004C44F, Instruction=FB, OReg= B, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=80000090, WPtr[0]=80000002
Out. Channel 800000A0, length 1, from memory at 80000090
Interrupting a LoPriority process.
Returning to interrupted LoPriority process.
IPtr=8004C450, Instruction=24, OReg= 4, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C451, Instruction=F3, OReg= 43, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=80000090, WPtr[0]=80000003
alt: (W-3)=Enabling_p
IPtr=8004C452, Instruction=11, OReg= 1, AReg= 1,
BReg=800000A0, CReg=80000090, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C453, Instruction=41, OReg= 1, AReg=80000094,
BReg= 1, CReg=800000A0, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C454, Instruction=24, OReg= 4, AReg= 1,
BReg=80000094, CReg= 1, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C455, Instruction=F8, OReg= 48, AReg= 1,
BReg=80000094, CReg= 1, WPtr=80000090, WPtr[0]=80000003
enbc(1): Channel 80000094
enbc(2): Waiting internal channel: (W-3)=Ready_p
IPtr=8004C456, Instruction=24, OReg= 4, AReg= 1,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=80000003
IPtr=8004C457, Instruction=F4, OReg= 44, AReg= 1,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=80000003
altwt(1): (W)=NoneSelected_o
altwt(2): (W-3) is 80000003
IPtr=8004C458, Instruction=60, OReg= 0, AReg= 1,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=FFFFFFFF
IPtr=8004C459, Instruction=7E, OReg=FFFFFFFE, AReg= 1,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=FFFFFFFF
IPtr=8004C45A, Instruction=23, OReg= 3, AReg=40D2F279,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=FFFFFFFF
IPtr=8004C45B, Instruction=FC, OReg= 3C, AReg=40D2F279,
BReg= 1, CReg= 1, WPtr=80000090, WPtr[0]=FFFFFFFF
IPtr=8004C45C, Instruction=21, OReg= 1, AReg=80000090,
BReg= 1, CReg= 1, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C45D, Instruction=7C, OReg= 1C, AReg=80000090,
BReg= 1, CReg= 1, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C45E, Instruction=21, OReg= 1, AReg= 0,
BReg=80000090, CReg= 1, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C45F, Instruction=7F, OReg= 1F, AReg= 0,
BReg=80000090, CReg= 1, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C460, Instruction=33, OReg= 3, AReg= 0,
BReg= 0, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C461, Instruction=F2, OReg= 2, AReg=80000000,
BReg= 0, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C462, Instruction=21, OReg= 1, AReg=80000000,
BReg=80000090, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C463, Instruction=7F, OReg= 1F, AReg=80000000,
BReg=80000090, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C464, Instruction=E3, OReg= 3, AReg= 0,
BReg=80000000, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C465, Instruction=21, OReg= 1, AReg=80000090,
BReg=80000000, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C466, Instruction=7D, OReg= 1D, AReg=80000090,
BReg=80000000, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C467, Instruction=21, OReg= 1, AReg= 0,
BReg=80000090, CReg=80000000, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C468, Instruction=7F, OReg= 1F, AReg= 0,
BReg=80000090, CReg=80000000, WPtr=40D2F279, WPtr[0]= 0
IPtr=8004C469, Instruction=34, OReg= 4, AReg= 0,
BReg= 0, CReg=80000090, WPtr=40D2F279, WPtr[0]= 0
In the correctly working code (extract 1) it appears that when
IPtr=8004C45C is reached the code continues running with the workspace
of the original low pri task, but now at high priority? Hmm
Questions.
I’m pretty sure that I’ve got the code correct and handing the
interrupt mechanism. I've spent ages debugging it now. It appears that
the D7205 oc (Inmos occam compiler) will only successfully run if the
high priority interrupting is disabled.
Is there a mechanism in the T414 (i.e. the actual silicon such as a
register?) to either disable the interrupting of a low priority
process by a high priority process, or maybe a means of changing the
interrupting mode so that the high priority task is put on the queue
and only started when the low priority process reached its next
rescheduling instruction. I’ve looked through all the
comp.sys.transputer but can’t find anything even close.
If there was something like this it might explain why the real T414
silicon happily runs the oc, whereas the T414 emulator hangs when the
high priority interrupting is enabled.
Gavin
Gavin...@ultracontrols.aero
the extract 2, that the code execution was identical to that in
extract 1.
Gavin
Mike B.
After the low priority process has completed his out instruction
(Iptr=#8004C44F) the high prioirty process should continue because he
is ready.
But listing 2 says: Returning to interrupted LoPriority process.
I think that's wrong.
OK: IPtr=8004C44F, Instruction=FB, OReg= B, AReg= 1
OK: Out. Channel 800000A0, length 1, from memory at 80000090
OK: Interrupting a LoPriority process.
??: Returning to interrupted LoPriority process.
??: IPtr=8004C450, Instruction=24, OReg= 4, AReg= 1
??: IPtr=8004C451, Instruction=F3, OReg= 43, AReg= 1
??: alt: (W-3)=Enabling_p
should be:
OK: IPtr=8004C44F, Instruction=FB, OReg= B, AReg= 1
OK: Out. Channel 800000A0, length 1, from memory at 80000090
OK: Interrupting a LoPriority process.
HI: IPtr=8004C458, Instruction=60, OReg= 0, AReg= 1
HI: IPtr=8004C459, Instruction=7E, OReg=FFFFFFFE, AReg= 1
HI: IPtr=8004C45A, Instruction=23, OReg= 3, AReg=80000090
My question is: In such a situation - should the low priority process
interrupted or descheduled?
-Mike
Mike B.
>interrupted or descheduled?
My question is: should the low priority process interrupted or on the
ready queue?
-Mike
Gavin...@ultracontrols.aero
Hello Mike,
According to the Inmos literature, a high priority process will be
run:
a). If there are no other high priority processes running (else it
will be queued);
b). At the completion of a low priority Inst (except for a couple that
are interruptible Insts – move etc.);
My interpretation of the above is that if a RUNP instruction is
executed to start a high priority task (from a low priority task),
then after the low priority task has completed, the high pri task
should start straight away (i.e. not requiring to be put on the queue
first).
Gavin
Mike B.
> My interpretation of the above is that if a RUNP instruction is
> executed to start a high priority task (from a low priority task),
> then after the low priority task has completed, the high pri task
> should start straight away (i.e. not requiring to be put on the queue
> first).
?????
> then after the low priority INSTRUCTION has completed, ...
From my point of view:
After the low priority process has completed his out instruction
(which set the alt state of the high priority process from Waiting.p
to Ready.p and reschedule the high priority process which is now
ready) the high process will run because altwt has been satisfied.
The out instruction of the low priority process will NOT transfer
data! This will be done by the alt construct in the disabling section.
Please refer to the section "Output to in channel in alt constructs"
in the Transputer Instruction Set.
Enabling.p P 0x80000001L
Waiting.p_P 0x80000002L
Disabling.p 0x80000003L
It is importend to have min. 4 link locations at the beginning of
memory because these values are invalid input channels addresses. This
allows the out instructions to detect alt enabled input channels.
This works because pw.pointer (-3) is at the same location as pw.state
(-3).
-Mike
Gavin...@ultracontrols.aero
I have relooked at the interrupted example and you are correct! There
is odd behaviour in that after the OUT instruction at IPtr = 8004C44F,
for some reason the alt waiting high pri process code does not get
run. Indicated by the odd behaviour of the interrupt to a low pri on
one line, followed on the next by a return to interrupted low pri.
I need to get the debugger on this and work out why the high pri task
(waiting on the alt) did not get restarted after the OUT instruction.
Gavin
Gavin...@ultracontrols.aero
> My interpretation of the above is that if a RUNP instruction is
> executed to start a high priority task (from a low priority task),
> then after the low priority task has completed, the high pri task
> should start straight away (i.e. not requiring to be put on the queue
> first).
> ?????
What I was trying to say was:
Assume a low priority process is running. Then assume it executes a
RUNP instruction which is to cause a high priority process to run.
This will either add it to the high pri queue, OR as I suspect (based
on the Inmos documentation) cause it to INTERRUPT and start the high
pri task, AFTER the current low pri task has completed.
Gavin
Mike B.
Please, can you report me the emulator performance with the IMS D7214C
"Hello World" benchmark?
icc hello /ta
ilink hello.tco /f startup.lnk /ta
icollect hello.lku /t
iserver /sr /ss /sc hello.btl
It would be interesting to know how fast an x86 CPU in 2009 can
emulate a transputer.
-Mike
Gavin...@ultracontrols.aero
I have some timing statistics for the Inmos Occam toolset (D7205A)
which I collected back in November 07.
Running the famous Knights Tour demonstration on the T414 emulator
using a PC laptop (spec below), and using an 8 by 8 chessboard,
starting at position (1, 1) it took 11 minutes to complete.
Laptop Spec: Intel Centrino Mobile Technology, Pentium M Processor 750
1.86 GHz, 2 MB L2 cache, 533 MHz FSB, 512Mb of RAM
Running the same set-up on a transputer board (Inmos B004 with a
T414B-15) in an old PC (486DX266) and it took 45 minutes to complete.
Hope this helps.
Gavin