Bit0 & Bit1 of the Transputer Wptr

[Mike B.]

The documentation about GAJW (general adjust workspace) says:
* Precond: Areg ^ byteselectmask = 0
or
* Areg should be word aligned
or
* If Areg is not word-aligned, its lower two bits are masked off so
that it is word-aligned

The test program which intentionally hurts the precondition shows
exact this, but then I rewrote my test program to use the constant
value 7 (and not the loop counter as previous) and a strange thing
happens:

#include <stdio.h>
#include <inline.h>
#include <limits.h>

int main( void ) {

unsigned long int *p = LONG_MIN;
int i;

p += 0x1C;

for ( i = 0; i < 12; i++ ) {
#pragma asm
ldc 7
gajw
gajw
mint
stnl 0x1C
#pragma endasm
printf( " 0x%08X\n", *p );
} /* endfor */

return 0;
}

C:\LSC-V89.1\test>ld-one wptr cio
LD-ONE (Single CPU Loader), Version 89.1
Copyright (c) 1986-1989 by Logical Systems

Loading A4h bytes of Transputer bootstrap code (T4 CPU)
Bootstrap loaded, awaiting reply
Bootstrap replied OK, downloading program 'wptr.tld'
Program downloading finished

CIO ('C' I/O Driver), Version 89.1
Copyright (c) 1986-1989 by Logical Systems

0x00000008
0x00000004
0x00000008
0x00000004
0x00000008
0x00000004
0x00000008
0x00000004
0x00000008
0x00000004
0x00000008
0x00000004

Any ideas why it is not always 0x00000004?

-Mike

[Gavin Crate]

> Any ideas why it is not always 0x00000004?

Hmm…I will have to load the C code example into the simulator to try
to fully understand what happening but looking at the example very
quickly it looks like the code is using MemStart (0x80000070) to hold
the value 0x4 after the gajw, gajw, mint and stnl. My guess is that
the first two word locations at the start of memory (i.e. 0x80000070,
0x80000074) are being used by the LEND instruction to perform the
loop?

It's just a guess and I will look at the simulator later to be sure.

Gavin