Cache implementation of MIPS processors
AVILA ALFONSO
Does anyone know where could I find documentation about the
cache implementation of the MIPS processors?
I am looking for information such as: cache size, block size, replacement
policies. I'd also like to know how the specifications of the hardware for
transfering a block from the cache to main memory and viceversa.
Thanks in advance for your help
Adios,
Alfonso
Kevin D. Kissell
>Does anyone know where could I find documentation about the
>cache implementation of the MIPS processors?
>
>I am looking for information such as: cache size, block size, replacement
>policies. I'd also like to know how the specifications of the hardware for
>transfering a block from the cache to main memory and viceversa.
The MIPS instruction set architecture does not specify the characteristics
(or even the existence) of caches, and by now there are a number of different
implementaions. The MIPS Technology guys in Mountain View have a Wep page,
http://www.mips.com, with pretty extensive information on most of them.
The latest MIPS CPU, the R10000, has separate 32K on-chip instruction and
data caches and a unified external secondary cache of 512K to 16M. Both
levels are piplined, non-blocking, and 2-way set associative. The primary
data cache has 32-byte lines, the secondary can have either 64 or 128 byte
lines. As the caches are write-back and non-blocking, replacement policy
is a bit complex, but all things being equal, it is LRU.
--
Opinions expressed may not be Kevin D. Kissell
those of the author, let alone Silicon Graphics Core Technology Group
those of Silicon Graphics. Cortaillod, Switzerland