A1-A23 for 24 bit address bus?
Patrick
challange for me, one thing I don't understand is how this bus is
called a 24 bit bus but only has 23 pins? I did not find another pin
that is taking on dual duty and acting as A0.
Could someone explain this to me?
Thanks in advance-Patrick
Robert Heller
The 68000 has a 16-bit databus -- it does not have byte addressing.
Instead of decoding A0 for odd/even bytes, there is are pins for low
and upper halfs of the 16 bit databus. 8-bit I/O devices are addressed
as even bytes (low-byte) or odd bytes (high-byte).
>
> Thanks in advance-Patrick
>
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Robert Heller
OK, I am home now and dug my MC68000UM[AD3]: "16-bit Microprocessor
User's Manual 3rd Edition" off my book shelf. On Page 34 is section
"4.2.3.3 Upper and Lower Data Scrobes (UDS, LDS)."
(Yes, this is for the original HMOS version, but the MC68HC000 is
logically the same.)
Basically, A0 is implied by the logic of UDS & LDS: UDS low implies A0
low (0), LDS low AND UDS high implies A0 high (1), and is only good for
8-bit transfers (at an odd address). UDS low and LDS high means
transfering a byte at an even address and both low means transfering a word
at an even address. It is only possible to transfer a word (16-bits) or
longword (32-bits) at an even address -- transfering a word (16-bits) or
longword (32-bits) at an odd address is illegal (see Page 68: 5.5.8
Address Error).
If you want to interface a 80xx style I/O chip (eg 8055 for example),
you use A1 for A0, A2 for A1 and A3 for A2, etc. and then use a a few
gates (7400's) to generate RD and WR from UDS or LDS (and use the
corresponding D8-D15 or D0-D7 for D0-D7) and R/W and use some sort of
timing logic to generate DTACK. The I/O ports are either at xxx0, xxx2,
xxx4, xxx6, xxx8, xxxA, xxxC, and xxxE (if using UDS) OR at xxx1,
xxx3, xxx5, xxx7, xxx9, xxxB, xxxD, and xxxF (if using LDS). 80xx I/O
chips expect a syncronous bus (which is what the
8080/Z80/8088/8086/80x86, etc. chips all are). The 68xxx chips use an
asyncronous bus. You *could* get seriously clever and use *both* UDS
and LDS to generate A0, but this is really far more hassle than it is
worth. There is no real reason not to just have the I/O chip use
successive even or odd addresses. There is usually plenty of address
space available.
(Transfering a longword (32-bits) is a two cycle operation with the
original 16-bit bus MC68000 and MC68HC000 processors.)
>
> Thanks in advance-Patrick
>
--
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Patrick
This is a really big help, I am going to print your response and keep
it nearby for the next few days
Thanks again-Patrick
Henk PA8PDP
news:g4Gdnc_SVt4y_4PR...@posted.localnet...
I would like to add that the M68k has a special instruction for addressing
"old" peripheral devices. Motorola understood that they should not forget
the 6800 series peripherals when they created the M68k.
(Yes, I am a fan of Motorola 6800/6809/68k processors).
When you wired A1 of the CPU to A0 of the peripheral device and use
either UDS* or LDS*, the device appears at even or odd addresses.
The MOVEP instruction deals with that just perfect!
- Henk, PA8PDP
tom_u...@optusnet.com.au
> In article <i85f7t$b1...@news.eternal-september.org>,
> "Henk PA8PDP" <henk.gooi...@hotmail.com> wrote:
> > > If you want to interface a 80xx style I/O chip (eg 8055 for example),
> > > you use A1 for A0, A2 for A1 and A3 for A2, etc. and then use a a few
> > > gates (7400's)
Or use a 6800 series chip connected to the 68000's E, VMA and VPA
signals. Pretty much glueless.
Assuming you can find a museum that you can get some of these chips
from :-).