Disabling cache memory on a 486/Pentium possible?

[Hans]

Is there anybody on this newsgroup who can tell me if it is possible to
disable the internal cache memory on a 486 or Pentium processor?

I am interested in evaluating these processors for space application.

One reason why these processors are not used in space is their unprotected
internal cache memory. However, if you can replace the internal cache with an
external hardware protected cache then the might be considered for LEO
applications.

thanks for your help,

Hans.

[Sonic]

It is possible to disable the 486's internal cache memory, this is
usually a BIOS option. There are however PD utilities that will do it.
Though I do not know how it is actually implemented in the silicon. It
depends what you mean when you say the cache is unprotected. Do you mean
unprotected logically or physically?

___ ___ _ __ __
// //_ //| | \ |_\ # <is: R.D....@Herts.ac.uk> # `Flibble i say,
\\__ __// __| |_/ | | # University of Hertfordshire # No 'tis Wierd'

[Christian Ludloff]

> It is possible to disable the 486's internal cache memory, this is
> usually a BIOS option. There are however PD utilities that will do it.
> Though I do not know how it is actually implemented in the silicon. It
> depends what you mean when you say the cache is unprotected. Do you mean
> unprotected logically or physically?

Switching the cache for i486 processors:

L1-cache on: CR0.CD=0 & CR0.NW=0
L1-cahce off: CR0.CD=1 & CR0.NW=1

Sometimes this has an effect on the external L2-cache too. :-(

Another way for iPentium processors:

L1-cache on: TR12.CE=0
L1-cache off: TR12.CE=1

Note: This has no effect on the CR0 register and no effect on the external
L2-cache. The TR12 register is the Model Specific Register #0Fh.

Note too: If you switch the cache state, you have to invalidate the cache
data. Otherwise the machine will hang, because the processor uses invalid
code or data from the cache, which was en/disabled by the user program.

Note also: Switching the cache is done different for IBM processors.

Just try my 4P package, which is described in my footer. It contains more
information and software too.

Christian

Christian Ludloff TEL ++49-371-242091 eMail c...@box.in-chemnitz.de
Ludwig-Kuehn-Str.15 FAX ++49-371-242091 eMail c...@vgasoft.com (new!)
D-09123 CHEMNITZ FIDO 2:2426/2240.14 Please, try the 4P package!

actual 4P package: ftp://ftp.tu-chemnitz.de/pub/Local/msdos/4p_v301.zip

## CrossPoint v3.02 ##

[Joel Sartoris]

In <ees1ht.9...@ee.surrey.ac.uk> ees...@ee.surrey.ac.uk (Hans)
writes:
>
>
>Is there anybody on this newsgroup who can tell me if it is possible

>to disable the internal cache memory on a 486 or Pentium processor?
>
>I am interested in evaluating these processors for space application.
>
>One reason why these processors are not used in space is their
>unprotected internal cache memory. However, if you can replace the
>internal cache with an external hardware protected cache then the
>might be considered for LEO applications.
>

I know its possible with the 486. Generally, the BIOS setup accommo-
dates enabling/disabling both the internal and external caches indivi-
dually. It can also be programmed by the user. One of the CPU control
registers (CR0, I believe) has a cache disable bit which can be set
("1" disables). You may also have to invalidate the cache contents to
completely disable it (INVD or WBINVD, I believe). Refer to any good
book on 486 programming, or "snoop" the BIOS with DOS DEBUG to see
how it's done.

--Joel Sartoris