I havent had the chance to drop in much, but I have been busy tinkering with II stuff in my spare time. Although its been at a snails pace, I have managed to prepare a prototype of Carte Blanche intended for the IIc (called CB Atto). Its a pretty tight fit and seems to just clear at the moment. There's still a long way to go with programming etc, but so far it feels like a good start and has passed all of its tests. I hope to see if Alex has the time to port JAT over to it at some point. Either way, its been an interesting experimental board.
> I havent had the chance to drop in much, but I have been busy > tinkering with II stuff in my spare time. Although its been at a > snails pace, I have managed to prepare a prototype of Carte Blanche > intended for the IIc (called CB Atto). Its a pretty tight fit and > seems to just clear at the moment. There's still a long way to go with > programming etc, but so far it feels like a good start and has passed > all of its tests. I hope to see if Alex has the time to port JAT over > to it at some point. Either way, its been an interesting experimental > board.
Raymond Wiker <r...@RAWMBP-2.local> writes: > Steve <srk...@gmail.com> writes:
>> Hi All,
>> I havent had the chance to drop in much, but I have been busy >> tinkering with II stuff in my spare time. Although its been at a >> snails pace, I have managed to prepare a prototype of Carte Blanche >> intended for the IIc (called CB Atto). Its a pretty tight fit and >> seems to just clear at the moment. There's still a long way to go with >> programming etc, but so far it feels like a good start and has passed >> all of its tests. I hope to see if Alex has the time to port JAT over >> to it at some point. Either way, its been an interesting experimental >> board.
> Will this work with the IIc+ as well as the IIc?
Hmmm... Answering my own question: "No". Looks like the CB Atto is meant to plug into a 40-pin DIL socket where the 6502 would normally be found; the IIc+ has a 68-pin(?) PLCC version of the 6502.
I may have to try to get hold of a IIc (or a IIe/II+) at some point, then :-)
> Raymond Wiker <r...@RAWMBP-2.local> writes: > > Steve <srk...@gmail.com> writes:
> >> Hi All,
> >> I havent had the chance to drop in much, but I have been busy > >> tinkering with II stuff in my spare time. Although its been at a > >> snails pace, I have managed to prepare a prototype of Carte Blanche > >> intended for the IIc (called CB Atto). Its a pretty tight fit and > >> seems to just clear at the moment. There's still a long way to go with > >> programming etc, but so far it feels like a good start and has passed > >> all of its tests. I hope to see if Alex has the time to port JAT over > >> to it at some point. Either way, its been an interesting experimental > >> board.
> > Will this work with the IIc+ as well as the IIc?
> Hmmm... Answering my own question: "No". Looks like the CB Atto > is meant to plug into a 40-pin DIL socket where the 6502 would normally > be found; the IIc+ has a 68-pin(?) PLCC version of the 6502.
> I may have to try to get hold of a IIc (or a IIe/II+) at some > point, then :-)
The IIc+ uses a 65C02 processor in addition to the custom ASIC. Compatibility aside, it remains to be seen if the socket for the ASIC will cause any clearance issues.
> I havent had the chance to drop in much, but I have been busy > tinkering with II stuff in my spare time. Although its been at a > snails pace, I have managed to prepare a prototype of Carte Blanche > intended for the IIc (called CB Atto). Its a pretty tight fit and > seems to just clear at the moment. There's still a long way to go with > programming etc, but so far it feels like a good start and has passed > all of its tests. I hope to see if Alex has the time to port JAT over > to it at some point. Either way, its been an interesting experimental > board.
In the IIc pictures it looks like that the MicroSD slots would not be easily accessible unless the base module was unplugged.
You might consider rotating the two outboard MicroSD sockets so that they point out to the ends. I also suggested in an email to you that it would be good to have the two inboard MicroSD sockets replaced with a 16x8 SDRAM chip (provided there's enough i/o available).
a2retro <a2retrosyst...@gmail.com> writes: > On Mar 27, 10:34 am, Raymond Wiker <r...@RAWMBP-2.local> wrote: >> Raymond Wiker <r...@RAWMBP-2.local> writes: >> > Steve <srk...@gmail.com> writes:
>> >> Hi All,
>> >> I havent had the chance to drop in much, but I have been busy >> >> tinkering with II stuff in my spare time. Although its been at a >> >> snails pace, I have managed to prepare a prototype of Carte Blanche >> >> intended for the IIc (called CB Atto). Its a pretty tight fit and >> >> seems to just clear at the moment. There's still a long way to go with >> >> programming etc, but so far it feels like a good start and has passed >> >> all of its tests. I hope to see if Alex has the time to port JAT over >> >> to it at some point. Either way, its been an interesting experimental >> >> board.
>> > Will this work with the IIc+ as well as the IIc?
>> Hmmm... Answering my own question: "No". Looks like the CB Atto >> is meant to plug into a 40-pin DIL socket where the 6502 would normally >> be found; the IIc+ has a 68-pin(?) PLCC version of the 6502.
>> I may have to try to get hold of a IIc (or a IIe/II+) at some >> point, then :-)
> The IIc+ uses a 65C02 processor in addition to the custom ASIC. > Compatibility aside, it remains to be seen if the socket for the ASIC > will cause any clearance issues.
Looks like I misread the wikipedia page on the IIc+ - the IIc+ has a 40-pin DIL version of the 6502. What I thought was the 6502 is the accelerator ASIC.
> I havent had the chance to drop in much, but I have been busy > tinkering with II stuff in my spare time. Although its been at a > snails pace, I have managed to prepare a prototype of Carte Blanche > intended for the IIc (called CB Atto). Its a pretty tight fit and > seems to just clear at the moment. There's still a long way to go with > programming etc, but so far it feels like a good start and has passed > all of its tests. I hope to see if Alex has the time to port JAT over > to it at some point. Either way, its been an interesting experimental > board.
Looks like something that might be a good addition to the //c. Of course the next question is the price, but I'm willing to wait to find out what it is.
> I havent had the chance to drop in much, but I have been busy > tinkering with II stuff in my spare time. Although its been at > a snails pace, I have managed to prepare a prototype of Carte > Blanche intended for the IIc (called CB Atto). Its a pretty > tight fit and seems to just clear at the moment. There's still > a long way to go with programming etc, but so far it feels like > a good start and has passed all of its tests. I hope to see if > Alex has the time to port JAT over to it at some point. Either > way, its been an interesting experimental board.
: : Looks like something that might be a good addition to the //c. : Of course the next question is the price, but I'm willing to : wait to find out what it is.
Looks like, from what I read on the site, it's a good addition to all Apple IIs and IIIs, except the IIgs, of course, unless... it can be adapted to plug into the 65816 socket. 8^)
On Mar 28, 7:16 am, "Bill Garber" <willy4...@garberstreet.com> wrote:
> Looks like, from what I read on the site, it's a good addition > to all Apple IIs and IIIs, except the IIgs, of course, unless... > it can be adapted to plug into the 65816 socket. 8^)
Excepting the lack of a freely available 65816 core, I see no reason why it wouldn't work just as well in a IIgs.
Also, this would make a perfect Zip Chip replacement should anyone add the necessary cache logic between the 65C02 core and the signals.
"mdj" <mdj....@gmail.com> wrote in message news:0346b6a6-
d229-4811-b701-7dbee5ddd...@x8g2000prh.googlegroups.com... On Mar 28, 7:16 am, "Bill Garber" <willy4...@garberstreet.com> wrote:
>> Looks like, from what I read on the site, it's a good addition >> to all Apple IIs and IIIs, except the IIgs, of course, unless... >> it can be adapted to plug into the 65816 socket. 8^) > Excepting the lack of a freely available 65816 core, I see > no reason why it wouldn't work just as well in a IIgs.
I thought so, considering all I've read on using 65C816 in a 65C02 based system.
> Also, this would make a perfect Zip Chip replacement should anyone > add the necessary cache logic between the 65C02 core and the signals.
Would this be possible while coding in 64K of the 1MB fast SRAM or the 4MB Flash (Also used to store the FPGA's bit stream) to use as the cache ram ???
> I havent had the chance to drop in much, but I have been busy > tinkering with II stuff in my spare time. Although its been at a > snails pace, I have managed to prepare a prototype of Carte Blanche > intended for the IIc (called CB Atto). Its a pretty tight fit and > seems to just clear at the moment. There's still a long way to go with > programming etc, but so far it feels like a good start and has passed > all of its tests. I hope to see if Alex has the time to port JAT over > to it at some point. Either way, its been an interesting experimental > board.
Steve,
As always, you do great work!
However, (and please take this as constructive criticism) it would be very helpful if some of that creative energy went into system documentation for the original CB. In particular, it's very difficult for a beginner in the field of HDL and FPGAs to get a foothold on the device. I'm sure all the details are there, but I would love to see some more high-level discussion of the CB architecture. For example:
- How does it map to the host bus and what would a basic interface scheme "look" like in terms of mapping logic to the symbolic port connections?
- Maybe a raw beginner's project that does something simple like embed 6502 code in a ROM area on the FPGA and permit it to be switched in and executed from the host.
- How does the ASIC adapter map to the FPGA? What would a "framework" that ties in a device on a that board look like and how are the pin connections referenced symbolically?
A lot of that information is probably implicit in Alex's designs, the schematics and the Xilinx databooks, but for the uninitiated the initial learning curve is quite steep. I've been sitting here with two boards for over a year and have not been able to negotiate it. I do have a reasonable amount of background in logic design, but it dates strictly from the TTL 74LS* era. There are just too many pieces that need to get sewn together at present for me to get a foothold, and I suspect it's been daunting for some others of us as well.
Anyway, sorry to sound critical. Maybe it's just me that's dense :-).
> > I havent had the chance to drop in much, but I have been busy > > tinkering with II stuff in my spare time. Although its been at a > > snails pace, I have managed to prepare a prototype of Carte Blanche > > intended for the IIc (called CB Atto). Its a pretty tight fit and > > seems to just clear at the moment. There's still a long way to go with > > programming etc, but so far it feels like a good start and has passed > > all of its tests. I hope to see if Alex has the time to port JAT over > > to it at some point. Either way, its been an interesting experimental > > board.
> Steve,
> As always, you do great work!
> However, (and please take this as constructive criticism) it would be very > helpful if some of that creative energy went into system documentation for the > original CB. In particular, it's very difficult for a beginner in the field > of HDL and FPGAs to get a foothold on the device. I'm sure all the details > are there, but I would love to see some more high-level discussion of the CB > architecture. > For example:
> - How does it map to the host bus and what would a basic interface scheme > "look" like in terms of mapping logic to the symbolic port connections?
> - Maybe a raw beginner's project that does something simple like embed 6502 > code in a ROM area on the FPGA and permit it to be switched in and executed > from the host.
> - How does the ASIC adapter map to the FPGA? What would a "framework" that > ties in a device on a that board look like and how are the pin connections > referenced symbolically?
> A lot of that information is probably implicit in Alex's designs, the > schematics and the Xilinx databooks, but for the uninitiated the initial > learning curve is quite steep. I've been sitting here with two boards for > over a year and have not been able to negotiate it. I do have a reasonable > amount of background in logic design, but it dates strictly from the TTL 74LS* > era. There are just too many pieces that need to get sewn together at present > for me to get a foothold, and I suspect it's been daunting for some others of > us as well.
> Anyway, sorry to sound critical. Maybe it's just me that's dense :-).
> Steve
Hi Steve,
I understand where you're coming from but maybe I am a little bit more comfortable with things as I have dabbled with the xilinx tools for a few CPLD projects. Logic design aside, the FPGA mounted on the CarteBlanche is same as any other CPLD/FPGA trainer out there.
It' simply a FPGA that has it's i/o's prewired to various hardware ports on the card. To understand how that relates to anything, you really need to study the schematic. Start by finding the page with host bus signals, follow them through the level translator chip to the particular pin on the FPGA. In order to use that information you need to make a UCF file (pin to signal map file) or ask someone who has already made one to give you a copy. There will be some signals in there that are constant (a2bus signals for example) and others that will be project dependent.
Once you understand that much, then you can start to think about how you might use those i/o's and the internal logic building blocks in a simple project.
I think your suggestion of emulating the onboard ROM of a peripheral card is a useful example and one that I want to know how to get working. I can think of a simpler first step and that is emulating registers for any peripheral card. So basically, be able to read data from the a2 bus, store it in a buffer and write it back when requested. Once you have that you can add ROM emulation. Take those two pieces and generate addressing/chip enablement to the on board SRAM and you have a 512K ram card.
If your game I'd be willing to work with you something like that (I've done it with a CPLD using ABEL).
On Mar 28, 5:26 am, a2retro <a2retrosyst...@gmail.com> wrote:
>. In order to use that information you need > to make a UCF file (pin to signal map file) or ask someone who has > already made one to give you a copy.
UCF for CB is available on the net somewhere... I have a copy. It tells you what pin on FPGA goes to which pins on: Apple II slot connector, IDE connector, video connector, etc.
"rich12345" <aiiad...@gmail.com> wrote in message news:8db25c
65-774e-4828-8738-7213a51bb...@k3g2000prl.googlegroups.com... On Mar 28, 5:26 am, a2retro <a2retrosyst...@gmail.com> wrote:
>> In order to use that information you need to make a UCF file >> (pin to signal map file) or ask someone who has already made >> one to give you a copy.
> UCF for CB is available on the net somewhere... I have a copy. > It tells you what pin on FPGA goes to which pins on: Apple II > slot connector, IDE connector, video connector, etc.
Here is the CB.UCF file:
#NET "SDO" LOC = "P87" | IOSTANDARD = LVCMOS33 ; #NET "SDI" LOC = "P61" | IOSTANDARD = LVCMOS33 ; #NET "SCL" LOC = "P103" | IOSTANDARD = LVCMOS33 ; # # SPI devices # #PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments NET "BUS_3M58" LOC = "P51" | IOSTANDARD = LVCMOS33 ; NET "BUS_7M" LOC = "P80" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<0>" LOC = "P4" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<10>" LOC = "P36" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<11>" LOC = "P39" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<12>" LOC = "P40" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<13>" LOC = "P47" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<14>" LOC = "P48" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<15>" LOC = "P49" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<1>" LOC = "P8" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<2>" LOC = "P11" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<3>" LOC = "P9" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<4>" LOC = "P12" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<5>" LOC = "P31" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<6>" LOC = "P33" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<7>" LOC = "P30" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<8>" LOC = "P23" | IOSTANDARD = LVCMOS33 ; NET "BUS_A<9>" LOC = "P22" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<0>" LOC = "P3" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<1>" LOC = "P5" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<2>" LOC = "P16" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<3>" LOC = "P19" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<4>" LOC = "P18" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<5>" LOC = "P29" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<6>" LOC = "P24" | IOSTANDARD = LVCMOS33 ; NET "BUS_D<7>" LOC = "P35" | IOSTANDARD = LVCMOS33 ; NET "BUS_DMA" LOC = "P41" | IOSTANDARD = LVCMOS33 ; NET "BUS_DMAIN" LOC = "P72" | IOSTANDARD = LVCMOS33 ; NET "BUS_DMAOUT" LOC = "P69" | IOSTANDARD = LVCMOS33 ; NET "BUS_INH" LOC = "P45" | IOSTANDARD = LVCMOS33 ; NET "BUS_INTIN" LOC = "P71" | IOSTANDARD = LVCMOS33 ; NET "BUS_INTOUT" LOC = "P68" | IOSTANDARD = LVCMOS33 ; NET "BUS_IOSTROBE" LOC = "P54" | IOSTANDARD = LVCMOS33 ; NET "BUS_IRQ" LOC = "P63" | IOSTANDARD = LVCMOS33 ; NET "BUS_NMI" LOC = "P65" | IOSTANDARD = LVCMOS33 ; NET "BUS_PHASE0" LOC = "P20" | IOSTANDARD = LVCMOS33 ; NET "BUS_PHASE1" LOC = "P26" | IOSTANDARD = LVCMOS33 ; NET "BUS_Q3" LOC = "P43" | IOSTANDARD = LVCMOS33 ; NET "BUS_R_W" LOC = "P50" | IOSTANDARD = LVCMOS33 ; NET "BUS_RDY" LOC = "P42" | IOSTANDARD = LVCMOS33 ; NET "BUS_RESET" LOC = "P60" | IOSTANDARD = LVCMOS33 | PULLUP ; NET "BUS_SYNC" LOC = "P57" | IOSTANDARD = LVCMOS33 ; NET "BUS_USER1" LOC = "P32" | IOSTANDARD = LVCMOS33 ; NET "h_sync" LOC = "P89" | IOSTANDARD = LVCMOS33 ; NET "IDE_ACT" LOC = "P189" | IOSTANDARD = LVCMOS33 | DRIVE = 2 ; NET "IDE_CS1" LOC = "P187" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<0>" LOC = "P93" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<1>" LOC = "P78" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<2>" LOC = "P167" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<3>" LOC = "P165" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<4>" LOC = "P164" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<5>" LOC = "P168" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<6>" LOC = "P147" | IOSTANDARD = LVCMOS33 ; NET "IDE_D<7>" LOC = "P133" | IOSTANDARD = LVCMOS33 ; NET "IDE_RES" LOC = "P153" | IOSTANDARD = LVCMOS33 | PULLUP; NET "N_BUS_DEV_SEL" LOC = "P14" | IOSTANDARD = LVCMOS33 ; NET "N_BUS_IO_SEL" LOC = "P204" | IOSTANDARD = LVCMOS33 ; NET "RGB<0>" LOC = "P145" | IOSTANDARD = LVCMOS33 ; NET "RGB<1>" LOC = "P146" | IOSTANDARD = LVCMOS33 ; NET "RGB<2>" LOC = "P140" | IOSTANDARD = LVCMOS33 ; NET "RGB<3>" LOC = "P144" | IOSTANDARD = LVCMOS33 ; NET "RGB<4>" LOC = "P83" | IOSTANDARD = LVCMOS33 ; NET "RGB<5>" LOC = "P150" | IOSTANDARD = LVCMOS33 ; NET "SD_CS" LOC = "P62" | IOSTANDARD = LVCMOS33 ; NET "SD_DET" LOC = "P58" | IOSTANDARD = LVCMOS33 ; NET "SOFT_TCK" LOC = "P184" | IOSTANDARD = LVCMOS33 ; NET "SOFT_TDI" LOC = "P159" | IOSTANDARD = LVCMOS33 ; NET "SOFT_TDO" LOC = "P113" | IOSTANDARD = LVCMOS33 ; NET "SOFT_TMS" LOC = "P154" | IOSTANDARD = LVCMOS33 ; NET "spi_rom_cs" LOC = "P55" | IOSTANDARD = LVCMOS33 ; NET "spi_sck" LOC = "P103" | IOSTANDARD = LVCMOS33 ; NET "spi_sdi" LOC = "P61" | IOSTANDARD = LVCMOS33 ; NET "spi_sdo" LOC = "P87" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<0>" LOC = "P206" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<10>" LOC = "P100" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<11>" LOC = "P102" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<12>" LOC = "P99" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<13>" LOC = "P134" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<14>" LOC = "P135" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<15>" LOC = "P138" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<16>" LOC = "P137" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<1>" LOC = "P126" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<2>" LOC = "P123" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<3>" LOC = "P122" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<4>" LOC = "P179" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<5>" LOC = "P84" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<6>" LOC = "P86" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<7>" LOC = "P197" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<8>" LOC = "P196" | IOSTANDARD = LVCMOS33 ; NET "SRAM_A<9>" LOC = "P186" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<0>" LOC = "P116" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<1>" LOC = "P163" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<2>" LOC = "P171" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<3>" LOC = "P90" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<4>" LOC = "P76" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<5>" LOC = "P120" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<6>" LOC = "P97" | IOSTANDARD = LVCMOS33 ; NET "SRAM_D<7>" LOC = "P129" | IOSTANDARD = LVCMOS33 ; NET "SRAM_NCS0" LOC = "P161" | IOSTANDARD = LVCMOS33 ; NET "SRAM_NCS1" LOC = "P119" | IOSTANDARD = LVCMOS33 ; NET "SRAM_NOE" LOC = "P127" | IOSTANDARD = LVCMOS33 ; NET "SRAM_NWE" LOC = "P94" | IOSTANDARD = LVCMOS33 ; NET "SYSCLK" LOC = "P183" | IOSTANDARD = LVCMOS33 ; NET "v_sync" LOC = "P77" | IOSTANDARD = LVCMOS33 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Followed by the Clock() add-on. These get inserted into the above file as necessary:
>> I havent had the chance to drop in much, but I have been busy >> tinkering with II stuff in my spare time. Although its been at a >> snails pace, I have managed to prepare a prototype of Carte Blanche >> intended for the IIc (called CB Atto). Its a pretty tight fit and >> seems to just clear at the moment. There's still a long way to go with >> programming etc, but so far it feels like a good start and has passed >> all of its tests. I hope to see if Alex has the time to port JAT over >> to it at some point. Either way, its been an interesting experimental >> board.
> Steve,
> As always, you do great work!
> However, (and please take this as constructive criticism) it would be very > helpful if some of that creative energy went into system documentation for > the original CB. In particular, it's very difficult for a beginner in the > field of HDL and FPGAs to get a foothold on the device. I'm sure all the > details are there, but I would love to see some more high-level discussion > of the CB architecture.
I too would like see more discussion. Sometimes I feel like I'm the only one doing anything with the CB and much of the time I'm lost. Still I have learned a little bit so maybe I can help.
> For example:
> - How does it map to the host bus and what would a basic interface scheme
> "look" like in terms of mapping logic to the symbolic port connections?
As Glenn mentioned, you start with the schematic (CBSCH01.pdf). Page 5 has the Apple II slot definition. If you follow any wire from the slot connector (yellow) to the column on the right (blue) you will see the name for that wire in the Carteblanche1 module. And as Glenn, Rich and Bill pointed out the names used are defined in the UCF (user constraints file). In the beginning of any module you write you enter the inputs and outputs by the names defined. For instance in the cb1.v (Carteblanche main module) file you have the "input BUS_3M58". Looking at the UCF you'll see 'NET "BUS_3M58" LOC = P51;', meaning BUS_3M58 is connected to pin 51 on the FPGA. Again looking at the schematic you'll see that BUS_3M58 is connected to pin 35 on the Apple II slot connector so pin 35 on the Apple is connected to pin 51 on the FPGA. Much of the work has already been done for you with the cb.ucf at least for the Apple II slot, the RGB output, the SD, etc.
As far as mapping logic to the symbolic port connections here is trivial Verilog example of what I think you mean:
/*---------------------------------------------*/ module test (input BUS_3M58, input BUS_PHASE0, input SYSCLK, output IDE_ACT); // SYSCLK is the onboard 14.31818MHZ oscillator reg do_something; // create a register to hold our logic
always@(posedge SYSCLK) // everytime the clock goes high begin do_something <= BUS_3M58 & BUS_PHASE0; // 'and' the 2 inputs & store result end
assign IDE_ACT = do_something; // output result to pin 16 of IDE connector endmodule /*--------------------------------------------*/
Disclaimer: I haven't tried this. It's just to give you some idea of how it works.
> - Maybe a raw beginner's project that does something simple like embed > 6502 code in a ROM area on the FPGA and permit it to be switched in and > executed from the host.
I've been thinking about doing something like this myself. I believe Alex does this for the floppy disk and z80 code, so there should be some ideas there. Incidentally, its very easy with the existing CB code to add the ability to *see* any peeks/pokes to any location in the IO area. This makes it nice to play around with your logic by pokeing values into unused IO locations.
> - How does the ASIC adapter map to the FPGA? What would a "framework" > that ties in a device on a that board look like and how are the pin > connections referenced symbolically?
I'm assuming the ASIC adapter is what is referred to in the schematics (page 7) as the Peripheral BD Interface. If so I believe you would use the UCF file to define the pins and symbols in the same way as the Slot connector is done.
> A lot of that information is probably implicit in Alex's designs, the > schematics and the Xilinx databooks, but for the uninitiated the initial > learning curve is quite steep.
I agree, I have been muddling around with this myself, but you just have to start with something and learn a little bit at a time.
> I've been sitting here with two boards for over a year and have not been > able to negotiate it.
I started by studying Alex's code and tentatively trying to change things. Most everything fails but occasionally I succeed and that feels good.
> I do have a reasonable amount of background in logic design, but it dates > strictly from the TTL 74LS* era. There are just too many pieces that need > to get sewn together at present for me to get a foothold, and I suspect > it's been daunting for some others of us as well.
You're way ahead of me there. I have very little knowledge of logic design, so I've had to try to learn that along with learning Verilog, FPGA's in general, the Carteblanche in particular and Xilinx's overwhelming tools. I also have found out that I know less about the hardware end of the Apple IIs than I thought I did.
Anyway, if I can help you get started just ask. Either email me or better yet ask here because I'm sure others will join in.
> Anyway, if I can help you get started just ask. Either email me or better > yet ask here because I'm sure others will join in.
Thanks for the kind offer, Charlie. I will try to screw up my courage to dive into this again. I got so frustrated last time around that I put all the pieces and docs away, so it will take a bit to get everything out, organized and ready for more work.
I still think there's a burning need for a raw beginners project that hand-holds the user all the way through - including basic negotiation of the Xilinx ISE dialogs. Maybe I'm asking for too much, so I'll stop before I sound like I'm whining :-).
One of my hopes was to synthesize a 6809 coprocessor board with the gen-u-ine CPU in the ASIC adapter. Alex had suggested this early on as a good candidate for schematic capture based synthesis. Not sure if he ever did it or not.
> > Anyway, if I can help you get started just ask. Either email me or better > > yet ask here because I'm sure others will join in.
> Thanks for the kind offer, Charlie. I will try to screw up my courage to dive > into this again. I got so frustrated last time around that I put all the > pieces and docs away, so it will take a bit to get everything out, organized > and ready for more work.
> I still think there's a burning need for a raw beginners project that > hand-holds the user all the way through - including basic negotiation of the > Xilinx ISE dialogs. Maybe I'm asking for too much, so I'll stop before I > sound like I'm whining :-).
> One of my hopes was to synthesize a 6809 coprocessor board with the gen-u-ine > CPU in the ASIC adapter. Alex had suggested this early on as a good candidate > for schematic capture based synthesis. Not sure if he ever did it or not.
> Steve
For anyone looking for beginner stuff, here are some other resources for general FPGA programming information
> > Anyway, if I can help you get started just ask. Either email me or better > > yet ask here because I'm sure others will join in.
> Thanks for the kind offer, Charlie. I will try to screw up my courage to dive > into this again. I got so frustrated last time around that I put all the > pieces and docs away, so it will take a bit to get everything out, organized > and ready for more work.
> I still think there's a burning need for a raw beginners project that > hand-holds the user all the way through - including basic negotiation of the > Xilinx ISE dialogs. Maybe I'm asking for too much, so I'll stop before I > sound like I'm whining :-).
There are plenty of tutorials for Xilinx ISE. The interface looks intimidating, but isn't once you watch the tutorials. Syntax of VHDL and Verilog isn't intimidating either, once you learn the languages (or just have a basic understanding of computer programming languages and boolean logic). Error reports can be confusing, but the ISE will search the web for a clear(er) description of errors.
> One of my hopes was to synthesize a 6809 coprocessor board with the gen-u-ine > CPU in the ASIC adapter. Alex had suggested this early on as a good candidate > for schematic capture based synthesis. Not sure if he ever did it or not.
It should be. The schematic is fairly simple. Putting a 6809 on board eliminates the need for a CPU IP core.
I think support/tutorial from Applelogic.org will never come, so we have to figure it out for ourselves...
Would be nice to set up a SKYPE chat where we can share knowledge and ideas.
> > Anyway, if I can help you get started just ask. Either email me or > > better > > yet ask here because I'm sure others will join in.
> Thanks for the kind offer, Charlie. I will try to screw up my courage to > dive > into this again. I got so frustrated last time around that I put all the > pieces and docs away, so it will take a bit to get everything out, > organized > and ready for more work.
> I still think there's a burning need for a raw beginners project that > hand-holds the user all the way through - including basic negotiation of > the > Xilinx ISE dialogs. Maybe I'm asking for too much, so I'll stop before I > sound like I'm whining :-).
> One of my hopes was to synthesize a 6809 coprocessor board with the > gen-u-ine > CPU in the ASIC adapter. Alex had suggested this early on as a good > candidate > for schematic capture based synthesis. Not sure if he ever did it or not.
> Steve
For anyone looking for beginner stuff, here are some other resources for general FPGA programming information
> I still think there's a burning need for a raw beginners project that > hand-holds the user all the way through - including basic negotiation of > the > Xilinx ISE dialogs. Maybe I'm asking for too much, so I'll stop > before I sound like I'm whining :-).
I agree with you there is a need. With 50 CB cards sold and only a handfull talking about it, I have to think there are many who don't know where to begin.
I have the 250 version of the CB. I don't think I have the skill to program it, but I'm very interested to try other peoples designs. One thing I do find upsetting is that the downloads on the CB page are different for the 500 and 250 variants...I can't help feel a little stiffed for having the 250.
It would be great to see the beta release of Soft Z80 Card, 6809 System 09/FLEX and OS, frogger, scramble and others available for the 250 also.
I know this is a small thing, but it would be nice.
>I have the 250 version of the CB. I don't think I have the skill to > program it, but I'm very interested to try other peoples designs. > One thing I do find upsetting is that the downloads on the CB page are > different for the 500 and 250 variants...I can't help feel a little > stiffed for having the 250.
Yeah, that's strange. I didn't know there were any 500s in the wild.
> It would be great to see the beta release of Soft Z80 Card, 6809 > System 09/FLEX and OS, frogger, scramble and others available for the > 250 also.
If the source code was available maybe they could be ported to the 250.
Wow, thanks for the feedback. Ill go through and see what I can answer;
--> Will this work with the IIc+ as well as the IIc?
The IIc+ had a PLCC socketed chip very close by, so I decided to exlcuded the IIc+ version just for the moment as it meant a lot of PCB mapping. But If a vote says the IIc+ must be included, I can come up with a crafty method to squeeze it in.
--> In the IIc pictures it looks like that the MicroSD slots would not be easily accessible unless the base module was unplugged.
Yes, it is rather tight. I put four micro SD cards in as these are pretty common and it was easy for me to do so. Giving better access can be arranged.
--> You might consider rotating the two outboard MicroSD sockets so that they point out to the ends.
I agree. However, with a board shape that suits all the decided hosts, this will determine what space is left. I dont want to design several different versions. Just the one atto.
--> also suggested in an email to you that it would be good to have the two inboard MicroSD sockets replaced with a 16x8 SDRAM chip (provided there's enough i/o available).
The MicroSD's dont affect memory. The memory is located on the cheap SODIMM FPGA module (these are current $60USD to have made in china) I have started a version with a 32MBx16 DRAM, so its is on the cards. The idea is to interchange to suit whats required. These modules are being used in other products, so I am piggy backing off their production.
--> Of course the next question is the price
I am targetting $170 for both boards.
--> except the IIgs, of course, unless... it can be adapted to plug into the 65816 socket
Yes. Clocking routes have been provided for the extra 65C816 pins. I havent got a core though.
--> Would this be possible while coding in 64K of the 1MB fast SRAM to use as the cache ram.
Yes, If the 1MB SRAM was a 32MB DRAM, you could still use it as a cache as the connection to the FPGA is private (its actually two 512k x8 blocks with optional 16 bit access)
--> if some of that creative energy went into system documentation for the original CB.
I did a ton of this for the Altium software I used to create the original CB, but no one used it. Altium designer just isnt that popular and I dont know ISE well enough to create the same sort of docco and examples. All details an be download from the slow applelogic site. I was hoping others might help here a bit.
--> It would be great to see the beta release of Soft Z80 Card, 6809 System 09/FLEX and OS, frogger, scramble and others available for the 250 also.
The Z80 i never finsihed - but ill post the source, however, its in Altium designer. ALex gave me the source to the 09/FLEX. Ill ask if its ok to post on the site. Ill see if I can round up the source to the others (which I think is in ISE), which where done by Mark and Red (The PACE guy's)
--> If the source code was available maybe they could be ported to the 250
I dont think so - the 250 lacks the internal SRAM if i recall correctly. No one really contemplated putting an arcade machine in carte blanche. The 250 can be upgraded to a 500 by simply replacing the FPGA chip. I may offer to do this if there is enough interest.
The FPGA domain has so much capability, but there are very few people who know it well enough or have the time to create some cool gear. Its also hard getting groups working on the one project to finish something. On the other hand there is an ample army of solo coders who can write apple II code simulators on platforms like the PC and linux boxes. So I created this little board as an experiment. An ARM interfaced to a IIe.(.. or II/III anything) so I can execute an apple II simulator inside the apple II.
Its a gumstix module (www.gumstix.com) that has its L3 to L4 front side bus (AHB) interfaced to the Apple IIe as if it where the 6502 processor. With wait enabled, it operates at exactly 1.023MHz (gated to apples sys clock), but can be tweeked to operated at up to 30MHz (but things start to stop). The Processor is a 700MHZ texas instruments OMAP 3530 apps processor with an ARM Cortex A8 CPU. Although this seems just plane wrong, I wanted to start to experiment with applications such as KEGS or Apple Win to see if this is a better way to expand and add life to these great machines. Anyway, its only an idea at this stage - and if I did it for a reason, it wouldnt be a hobby. :)
> --> if some of that creative energy went into system documentation for > the original CB.
> I did a ton of this for the Altium software I used to create the > original CB, but no one used it. Altium designer just isnt that > popular and I dont know ISE well enough to create the same sort of > docco and examples. All details an be download from the slow > applelogic site. I was hoping others might help here a bit.
It's not a matter of popular so much as a matter of "free" vs. huge bucks. Altium looks terrific, but as a hobby I cannot rationalize the expense. ISE is free-as-in-beer.
> --> If the source code was available maybe they could be ported to the > 250
> I dont think so - the 250 lacks the internal SRAM if i recall > correctly. No one really contemplated putting an arcade machine in > carte blanche. The 250 can be upgraded to a 500 by simply replacing > the FPGA chip. I may offer to do this if there is enough interest.
I would take you up on that service. Although I recently purchased a hot-air rework station and have the correct nozzle for the FPGA chip, I'm a bit scared to have at it with my limited experience. Probably better if I stick to practicing on dead PC motherboards for the time being :-).
On Apr 1, 6:57 am, Steve <srk...@gmail.com> wrote:
> Hi all,
> Wow, thanks for the feedback. Ill go through and see what I can > answer;
...
> --> You might consider rotating the two outboard MicroSD sockets so > that > they point out to the ends.
> I agree. However, with a board shape that suits all the decided hosts, > this will determine what space is left. I dont want to design several > different versions. Just the one atto.
That's understandable. :)
> --> also suggested in an email to you that it would be good to have > the two inboard MicroSD sockets replaced with a 16x8 SDRAM chip > (provided there's enough i/o available).
> The MicroSD's dont affect memory. The memory is located on the cheap > SODIMM FPGA module (these are current $60USD to have made in china) > I have started a version with a 32MBx16 DRAM, so its is on the cards. > The idea is to interchange to suit whats required. These modules are > being used in other products, so I am piggy backing off their > production.
I wasn't sure if you had designed the FPGA module or it was coming from somewhere else. That's why I suggested replacing 2 of the MicroSd slots with a SDRAM on the base board if you didn't have control over the FPGA module. SDRAM on either board would be great.
