On Thu, 06 Sep 2012 01:09:26 +0100, Rui Maciel <
rui.m...@gmail.com>
wrote:
There are no fully satisfying definitions for the word size of the
machine (and there are machines for which a definition is almost
impossible), but the size of the GP registers is probably the best.
Virtual address size is particularly unsatisfying. Consider x86-32,
which arguably has two levels of virtual addressing, segmented
addresses and linear addresses, the former are 46 or 48 bits, and the
later 32. Intel could fairly easily have increased the linear address
space. And virtual addressing is perfectly possible with just x86
segmentation (as demonstrated by a number of x86-16 protected mode
OSs), and a OS that allowed swapping ~16K 512MB segments would have
been perfectly plausible (although swapping such a large segment to
disk would be painful, so say the least).
Or consider S/360. The original ISA had 32 bit registers and
operations, but 24 bit addressing - and not just because they ignored
the high eight bits*. With XA mode, they introduced a 31 bit
addressing mode (again there were places the high bit** was put to
use). You really wouldn't call the ISAs 24 or 31 bit***.
Likewise many of the 8-bitters had no 16 bit registers, but could
address much more than 256 bytes of memory (64KB being common) - no
one would ever call them 16 bit processors for that reason.
ALU width or memory data bus width have been used too, and are even
worse choices.
*For example, the subroutine call instructions stored data in the high
byte, several instructions were defined to affect the high byte in
non-address ways, and address space wrap-around was architected as
happing after (2**24-1).
**For example, the high bit was stored and used by subroutine
call/return instructions in calls between 24 and 31 bit code to save
and restore the mode. In 64 bit mode, the *low* bit of program
addresses is used (as instructions have to be halfword aligned) to
indicate that mode vs. 24/31 addresses. So in 64 bit mode BASSM
(branch and save and set mode) would look at the low bit of the 64 bit
target address register to see if it's branching to 64 bit code, and
if not, then the high bit of the "32 bit" address to distinguish
between 31 and 24 bit code), and then the *current* mode is saved
along with the return address in the specified return address
register.
***Although it's common to refer to 24, 31 or 64 bit programs in that
world.