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About x86 and ARM and M1 processors..
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Amine Moulay Ramdane
Jan 15, 2021, 2:54:15 PM1/15/21
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Hello,
About x86 and ARM and M1 processors..
I have just noticed that Apple has just released the M1 processor and it is
ARM-based, here it is:
https://www.theverge.com/2020/11/19/21574057/apple-m1-chips-laptop-performance-intel-qualcomm-competition
But i think this ARM-based processor uses WMO hardware memory
model, but i think the WMO hardware memory model is dangerous to
program with(such as synchronization algorithms), also look here at the RISC-V processor that supports both TSO and WMO hardware memory models, and it says that RISC-V TSO hardware memory model is as fast as RISC-V WMO memory model, read here:
https://riscv.org/wp-content/uploads/2019/06/16.15-Stefanos-Kaxiras.pdf
So i think that ARM processors are not smart since they have to support both TSO and WMO memory models like RISC-V.
About SC and TSO and RMO hardware memory models..
I have just read the following webpage about the performance difference
between: SC and TSO and RMO hardware memory models
I think TSO is better, it is just around 3% ~ 6% less performance
than RMO and it is a simpler programming model than RMO. So i think ARM
must support TSO to be compatible with x86 that is TSO.
Read more here to notice it:
https://infoscience.epfl.ch/record/201695/files/CS471_proj_slides_Tao_Marc_2011_1222_1.pdf
About memory models and sequential consistency:
As you have noticed i am working with x86 architecture..
Even though x86 gives up on sequential consistency, it’s among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.
ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.
Read more here:
https://homes.cs.washington.edu/~bornholt/post/memory-models.html
Memory Models: x86 is TSO, TSO is Good
Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.
The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.
Read more here:
https://jakob.engbloms.se/archives/1435
Thank you,
Amine Moulay Ramdane.
About x86 and ARM and M1 processors..
I have just noticed that Apple has just released the M1 processor and it is
ARM-based, here it is:
https://www.theverge.com/2020/11/19/21574057/apple-m1-chips-laptop-performance-intel-qualcomm-competition
But i think this ARM-based processor uses WMO hardware memory
model, but i think the WMO hardware memory model is dangerous to
program with(such as synchronization algorithms), also look here at the RISC-V processor that supports both TSO and WMO hardware memory models, and it says that RISC-V TSO hardware memory model is as fast as RISC-V WMO memory model, read here:
https://riscv.org/wp-content/uploads/2019/06/16.15-Stefanos-Kaxiras.pdf
So i think that ARM processors are not smart since they have to support both TSO and WMO memory models like RISC-V.
About SC and TSO and RMO hardware memory models..
I have just read the following webpage about the performance difference
between: SC and TSO and RMO hardware memory models
I think TSO is better, it is just around 3% ~ 6% less performance
than RMO and it is a simpler programming model than RMO. So i think ARM
must support TSO to be compatible with x86 that is TSO.
Read more here to notice it:
https://infoscience.epfl.ch/record/201695/files/CS471_proj_slides_Tao_Marc_2011_1222_1.pdf
About memory models and sequential consistency:
As you have noticed i am working with x86 architecture..
Even though x86 gives up on sequential consistency, it’s among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.
ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.
Read more here:
https://homes.cs.washington.edu/~bornholt/post/memory-models.html
Memory Models: x86 is TSO, TSO is Good
Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.
The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.
Read more here:
https://jakob.engbloms.se/archives/1435
Thank you,
Amine Moulay Ramdane.
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