--Yang
If you are going to be doing lock-free programming, you will need
to understand that the primitives involved are not portable between
different CPU architectures.
For example, MIPS systems don't have CAS, but rather a
load-linked/conditional-store instruction pair. It's been long enough
since I touched a SPARC that I've now forgotten what synch primitives
are available there. You will need to concern yourself with what order
memory accesses become visible to other processors, and those details
change with each architecture (and often within implementations of an
architecture!).
You are entering an area that's surprisingly complex. Unless you have
compelling evidence that you need lock-free techniques, I would suggest
avoiding them at the application level, and using the primitives the
system provides.
If you plan on writing an API layer for your lock-free queues (or
whatever), there's a couple of other recent threads (pun not intended)
in this newsgroup that might get you started.
--
Steve Watt KD6GGD PP-ASEL-IA ICBM: 121W 56' 57.8" / 37N 20' 14.9"
Internet: steve @ Watt.COM Whois: SW32
Free time? There's no such thing. It just comes in varying prices...
Microsoft provides CAS-like functionality via its
InterlockedCompareExchange function. Another option is to write inline
assembler, though this is obviously nonstandard. I'm not aware of any
cross-platform APIs to do this, though I'm sure they must exist.
Sean
Check out the atomic_ops package here
http://www.hpl.hp.com/research/linux/qprof/
--
Joe Seigh
When you get lemons, you make lemonade.
When you get hardware, you make software.