[ecsi-2] ESLsyn > Early registration deadline today! Preliminary Program > Electronic System Level Synthesis Conference > co-located with DAC!

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ESLsyn
May 31 - June 1, 2013
Austin, TX, USA
www.ecsi.org/eslsyn<http://www.ecsi.org/eslsyn>
Co-located with DAC!

General Chair
Achim Rettberg,
University of Oldenburg,
Germany

Early Registration Deadline: May 6!

Demonstration & Sponsorship Opportunities!
Contact us at eslsy...@ecsi.org<mailto:eslsy...@ecsi.org> for details

Demonstrations & Sponsorship Opportunities!
Demonstration of tools will be possible at the conference for ECSI Members and ESLsyn Conference Sponsors. They will benefit from:
* Access to a demonstration booth composed of a poster stand and a table with power outlets
* Access to the list workshop registrations
* Publicity opportunities
* 1 Free Registration
Contact us at eslsy...@ecsi.org<mailto:eslsy...@ecsi.org> to find out more about Membership benefits and Sponsorship opportunities!
Preliminary Program

Friday, May 31

Keynote 1: tbc

Session 1: High-Level Synthesis

Partial Controller Retiming in High-Level Synthesis

Ryoya Sobue (Ritsumeikan University), Yuko Hara-Azumi (Nara Institute of Science and Technology) and Hiroyuki Tomiyama (Ritsumeikan University)

System Level Synthesis Of Dataflow Programs: HEVC decoder case study

Mariem Abid, Khaled Jerbi, Mickael Raulet, Olivier Deforges (INSA of Rennes) and Mohamed Abid (ENIS Sfax)

Synthesis and Optimization of High-Level Stream Programs

Endri Bezati, Simone Casale Brunet, Marco Mattavelli (EPFL SCI-STI-MM) and Jorn Janneck (Lund University)

Invited Presentation 1

Automatic Prototyping of declarative properties on FPGA

Dominique Borrione (TIMA, France)

Invited Presentation 2

Precision Timed Infrastructure: Design Challenges

David Broman, UC Berkeley

Session 2: Work-in-Progress

Automatic Partitioning of Behavioral Descriptions for High-Level Synthesis with Multiple Internal Throughputs

Benjamin Carrion Schafer (The Hong Kong Polytechnic University)

From Multicore Simulation to Hardware Synthesis Using Transactions

Amine Anane and El Mostapha Aboulhamid (Université de Montréal)

Efficient Preemption of Loops for dynamic HW/SW partitioning on Configurable Systems on Chip

Marko Roessler, Ulrich Heinkel and Jan Langer (Chemnitz University of Technology)

EDA Synthesis Tools Presentation & Demos

Saturday, June 1

Keynote 2: Professor Arvind, MIT

Session 3:System Level Modeling & Synthesis

Scalable High Quality Hierarchical Scheduling

Wei Tang and Forrest Brewer (University of California, Santa Barbara)

Multi-Core Cache Hierarchy Modelling for Host-Compiled Performance Simulation

Parisa Razaghi and Andreas Gerstlauer (The University of Texas at Austin)

Pre- and Post-Scheduling Memory Allocation Strategies on MPSoCs

Karol Desnos, Maxime Pelcat, Jean-François Nezan (IETR, INSA de Rennes, CNRS UMR 6164, UEB) and Slaheddine Aridhi (Texas Instruments France)

Invited Presentation 3

Title TBC

Jorn W. Janneck, Lund University

Invited Presentation 4

System Synthesis from UML/MARTE Models: The PHARAON approach

Eugenio Villar, University of Cantabria

Panel Discussion

Program Co-Chairs
Andreas Gerstlauer,
University of Texas, Austin, USA
Marcio Kreutz,
Federal University of Rio Grande do Norte, Brazil
Organization Chair
Adam Morawiec,
ECSI, France

Program Committee

David Black, Doulos

Jens Brandt, TU Kaiserslautern

Benjamin Carrion Schafer,

Hong Kong Polytechnic U.

Patricia Derler, UC Berkeley

Abdoulaye Gamatie, LIFL

Thierry Gautier, IRISA

Christoph Grimm,

TU Kaiserslautern

Kim Grüttner, OFFIS

Yuko Hara-Azumi,

Nara Institute of Science

and Technology

Christian Haubelt,

U.of Erlangen-Nürnberg

Niraj K. Jha,

Princeton University

Taemin Kim, Intel

Luciano Lavagno,

Politecnico di Torino

Frédéric Mallet, INRIA

Adam Morawiec, ECSI

Stephen Neuendorffer, Xilinx

Bernhard Niemann, Fraunhofer

Hiren Patel,

University of Waterloo

Dumitru Potop-Butucaru,

INRIA

Doemer Rainer, UC Irvine

Eric Rutten, INRIA

Sandeep Shukla, Virginia Tech

Andres Takach, Calypto

David Thomas,

Imperial College London

Hiroyuki Tomiyama,

Ritsumeikan University

Eugenio Villar,

University of Cantabria

Zhiru Zhang,

Cornell University

Contacts

www.ecsi.org/eslsyn<http://www.ecsi.org/eslsyn>

eslsy...@ecsi.org<mailto:eslsy...@ecsi.org>

ESLsyn

is organized with the technical co-sponsorship of CEDA.

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