On 2013-05-22 12:13:12 +0000,
johnso...@gmail.com said:
> When it comes to writing a new ethernet driver, I believe the core work
> that needs to be done is to present a driver that complies with the needs
> of VCI, which is the kernel mode API that the network stacks program against.
>
> I think this convergence piece is far more difficult to implement.
> I would expect the need for broader kernel level changes in order toget
> a unified driver to deal with kernel code for storage and kernel code
> for networking. VCI is only for the unification of network access. I
> don't think there's such a thing for storage.
AFAIK, all Fibre Channel host bus adapter devices supported on OpenVMS
use a class-and-port interface to connect into the Fibre-SCSI device
driver stack.
The Fibre/SCSI class driver (DG/DK) deals with the high-level pieces
and user-facing pieces of the I/O, while the port drivers deal with the
lower-level pieces and the hardware.
There's also what's known as an ALTSTART interface into the Fibre/SCSI
device driver stack, and packages and tools with kernel-mode code —
such as LD — use that interface to communicate with the device drivers.
The classic ALTSTART interface — available on a number of device
drivers, whether that was documented or not — is the rough analog to
the VCI interface.
But in any case, both Fibre/SCSI port drivers and the network port
drivers can be quite complex drivers.
Combining storage and networking into a single hardware interface has
been done before, with the DEPVZ and KZPCM adapters and potentially
others. The relative difficulties and likely issues here are dependent
on the interface and operation of the particular hybrid adapter
reportedly involved, too. (Various of the newer-generation adapters
I've worked with intentionally presented hardware interfaces that were
compatible with earlier-generation hardware by default, to ease the
effort of adding software support. Drivers could then be updated to
add support for newer features latent in the newer-generation
interfaces. But YMMV.)
Poulson is the biggest change to the Itanium series architecture, too.
Poulson also adds some out-of-order capabilities and reportedly changes
to the hyperthreading, and I don't know off-hand if there are any areas
of OpenVMS or application code that might be effected by that. That'd
definitely require some kernel folks and some compiler folks "crawling
through" all the details of those changes, specifically around
synchronization, probably also around the details of cache handling.
Whether any of the new error detection and correction features need
handlers would also need some investigation; I'd expect at least a
requirement to add some error-logging support.
Compilers can or will need some tweaks to use what's now available,
too. The existing code generators may (will?) continue to work, but
I'd expect there will be various advantages gained from adding support
for at least some of the changes. This was the general case with code
generation for newer-generation Alpha processors, too.
The OpenVMS ACPI code would likely need tweaks to deal with however the
Poulson boxes are presenting themselves to the host software.
One other related OpenVMS kernel API detail (limit) that I haven't been
able to independently confirm: the OpenVMS scheduler was limited to 64
cores/hyperthreads due to the scheduler's use of quadwords, and I don't
know if that was reworked with V8.4. There were changes implemented to
extend the user-visible portions of some related APIs to allow for
these (potential) kernel-mode changes, particularly with the
deprecation of the SYI$_*_MASK $getsyi itemcodes and the migration to
SYI$_*_BITMAP itemcodes (eg: deprecated SYI$_ACTIVE_CPU_MASK to
SYI$_ACTIVE_CPU_BITMASK) , but I don't know if any kernel-mode changes
were implemented in the scheduler itself. The Alpha V7.0 subset-IDSM
book references only quadwords. If these scheduling changes were not
implemented, then there'd be a few more changes necessary to add
support, or OpenVMS would be limited to four-socket boxes or equivalent
VM guests with Poulson; that'd be the rx2800 i4, BL860c i4, or BL870c
i4, and nothing larger. (Assumption: Four sockets, eight cores per
socket, two hyperthreads per core, one quadword chock-full of bits.)
Then there's the question of whether typical application loads would
perform adequately with more than 64 cores / hyperthreads, or if the
box would end up just "spinning" the extra processing resources behind
some spinlock or mutex. That's happened before as OpenVMS SMP support
has been scaled up, and finding and addressing performance bottlenecks
tends to be an incremental software re-engineering process.
Ancillary tools such as MONITOR, SHOW CPU, T4 and other integrated or
add-on system-performance and system-monitoring tools would need at
least a cursory look, just to see what happens with more than 64 cores
/ hyperthreads active. If those tools have processor bitmasks stored
in log files, those too can need changes. Any source code with
SYI$_*_MASK warrants a look, too.
Would adding this hardware support be possible? Technically, yes. I'd
definitely expect that adding support for Poulson would be possible.
But would that support be trivial to implement? I'd expect not. Will
application code need changes? Some code might, particularly if the
application code encounters more than 64 hyperthreads and reacts
inappropriately. I'd also wonder whether the changes in the
instruction processing might also trigger some OpenVMS- or
application-level issues, akin to what happened with the invalid Alpha
object code that was being generated a while back. (qv: SRM_CHECK.)
And who knows what other wrinkles might lurk here; there are always
errata.
Put another way, AFAIK adding Poulson support would not be quick, nor
cheap. I have no doubt that HP has a very good idea of what is
involved here, too.
The above is entirely technical speculation, and based solely on
published details.
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