On Mon, 15 Apr 2013,
monah...@gmail.com wrote:
> I would like to mention that Andrew Lynch and I have just completed work
> on the final prototype (V4!) of a new 80386 Master/Slave CPU S-100 bus
> board. This board is capable of reaching up to36MHz for its clock input
> when used with RAM on its daughter board (see below).
>
> For those that have been following progress this has been a long
> project. It utilizes the 16 bit mode of the 80386 to address up to the
> 16MG of RAM the S-100 bus is capable of addressing. A second daughter
> board system with two overhead ribbon cable connectors is utilized to
> allow 32 bit addressing to one or more RAM boards. This "32-Bit S-100
> Overhead Bus" as I call it, allows the CPU to run at its maximum speed
> (no wait states) and with the current static RAM chips in pipeline mode.
> The current daughter RAM board utilizes 16MG of static RAM. The plan is
> to next add high capacity DRAM boards.
>
> It turned out that the 80386 splices very nicely into the S-100 bus. The
> CPU control signals are clean and tolerant. In fact the interface is
> simplifier than our earlier 8086 and 80286 boards. No bus controller or
> clock generator chips for example are needed.
>
> The real fun in working with this chip is now one can take advantage of
> the 32 bit programming mode of the 80386 and its vast memory addressing
> capability. It took some time to understand how to switch the CPU into
> “protected mode” and I have written this up to make it easier who may
> like to start into this world for the first time.
To me, 386 is mainly useful for its ability to emulate stuff... it might