Discussions - comp.lsi.cad

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Ziphone: Latest Apple iPhone news!!!!

Ziphone updates you with all the latest apple iPhones news, by visiting this blog you will be able to enhance your knowledge about the latest iPhone applications and software launched by Apple and the ones that are in the pipeline. As you are now more aware about all latest iPhone applications so go ahead to use them in a better way on... more »

By alisha jones - Aug 26 - 1 new of 1 message

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Problem running systemC in Modelsim

Hi All, I got a problem running systemC in Modelsim. I'm using Modelsim 6.2j Ubuntu Linux platform x86_64. The modelsim-gcc plugin, which is gcc-4.0.2-linux_x86_64, was already installed. I managed to compile all codes, but failed when linked it (sccom -link). It came up with error message: /usr/lib/../lib64/libm.so: file not recognized: File format not recognized... more »

By Yan Syafri Hidayat - May 15 - 1 new of 1 message

	espresso logic minimizer
	hi, i try to install espresso logic minimizer in UNIX but when i compile with -make command- that's what i get: make: * No rule to make target `/net/shambhala/users/octtools -3.0/ lib/llib-lutility.ln', needed by `lint'. Stop. any one know how can i fix this. By hassan - Apr 23 - 1 new** of 1 message

In GDS format spec, is layer definition required to be immediately after beginning of an element?

Hi, I am writing a program to read and handle GDS files. In the GDS files that I have seen, layer definition has been always immediately after beginning of an element. See examples below. But I don't see the clear description in GDS format spec, about whether such sequence is required. If it is required by the spec, then my program would be much... more »

By Kuhl - Apr 11 - 1 new of 1 message

	Fundamentals of Digital Logic with VHDL by Brown Vranesic
	this book about digital design using vhdl language the link: [link] By eng.hossamanwar@gmail.com - Apr 10 - 1 new of 1 message

	Analog Cell Library Design
	I am working on a CMOS Analog Cell Library Design as a part of my Course. Can anyone please point out to useful resources if any one has worked on this and I believe some-one has ! Thanks and Regards By nicollete - Oct 13 2008 - 1 new of 1 message

	ERC Checking tools
	Hello I am trying to figure out if there is any tool available from EDA vendors or any individual projects that do netlist based Electrical Rule checking on schematic? Thank You By spyder - Aug 27 2008 - 2 new of 2 messages