Description:
VHSIC Hardware Description Language, IEEE 1076/87.
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abstract type signal
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Hi everyone!
I have a module, that makes some actions with signal S of the type myType. This actions with signal S is independent of its type.
For using this modules for signals of various types I create a copies of module with another name and "Find and replace" myType to MyOtherType.
I think that it is conceptually wrong way.... more »
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Signal xx cannot be synthesized, bad synchronous description error
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Hi
I need to make a kind of controller for a school project but i keep getting stuck on the same error. which is: "ERROR:Xst:827 - "D:/School/VHDL/ServoControlle r/ControllerBeta.vhd" line 132: Signal nextstate cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."... more »
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Asynchronous With Select and When Else Statements
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Hi everyone,
I am coding up a project to route and control Gigabit ethernet.
Basically the FPGA receives MDIO communication from Processor 1 or Processor 2( Both masters, only one can be master at a time).
The logic decides based on a priority and a keep alive signal which master controls the MDIO bus.... more »
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Counting number of asserted register bits in VHDL
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Hello,
I have a status register of width, R_SIZE. This is a generic so the register width may be different depending on the application. The R_SIZE is limited to values, 4, 8 and 16.
Each bit in the register is set by different module as an indication of that module's done status. These status bits are asserted for only one clock and may be asserted again as each module may run its application multiple times on different data.... more »
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Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs
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Dear Fellow Students and Researchers,
I am sharing one useful announcement for those who are interested in writing and publishing research papers in the field of Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs.
Please have a look to the following call for paper on Reconfigurable Computing.... more »
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Generics, packages, and VHDL-2008
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Hey y'all --
If I have an entity with a generic, call it DATA_WIDTH. And I want
that entity to use a package that has a DATA_WIDTH generic, in this
specific case the package provides for a queue, implemented on shared
variables, that the package would use.
Is there any way to call out the instantiated package using the... more »
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VHDL Standards Invitation and Status
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Hi, The VHDL Standards group is currently working on VHDL 1076-201X.
Currently we are working on developing language change proposals.
Check them out at: [link]
Did we miss something? Could the proposals be better?
Join us and help out. We have many tasks that can involve... more »
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verification strategy with no specs
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Dear all,
I've been appointed to review and verify a vhdl project of about 25k
lines of code, *without* a specification document!
There are various scattered notes/docs which describes somehow some
details (*not all*), but there's no description of what the individual
parts should do, even though there are only 4 types of FPGA in the system.... more »
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VHDL Model for a MIPS Processor
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If anyone is able to do the following for me, it would be appreciated. Please comment the code, since I am trying to learn how to do code in VHDL for the future.
1.Develop a VHDL model for the MIPS processor. The model should simulate a 4-stage (Fetch, Decode, Execute, and Write-back) pipeline design.... more »
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help for usb3300
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Hey every one does someone had use VHDL code to control USB3300 IC
to design Host and Device CHRIP
who can help thx every one
forgive me have poor English
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