Description:
VHSIC Hardware Description Language, IEEE 1076/87.
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Test process behaviour
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Hi,
I have used VHDL for some years but still get confused sometimes...
I have a testbench with a process calling a number of procedures. Each
procedure represents a test case. One procedure is supposed to inject
a fault by forcing a line low to see if fault flags are set in the
design. The problem is that this procedure mess up all remaining test... more »
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Why cant protected type methods have a parameter thats an access type?
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Yes I know "thems the rules", but I want to know why. Theres nothing
wrong with throwing access types around normal functions and
procedures, so why are protected types so special? There also the
issue I raised a long time ago - you're not allowed to make arrays of
protected types or pointers to them? Are they just trying to hobble... more »
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parallel CRC and ragged words
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I've been looking over the following post concerning parallel crc
computation and how to handle a multi-byte parallel bus where the data
can end in any 8b position:
[link]
All of the identities Allan calls out make perfect sense, except when... more »
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Active-HDL/Xilinx Core FIFO Gen Sim Problem
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Hi there,
I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I
used Aldec's design flow tools to implement a Coregen FIFO, and am
using a recent, manufacturer-compiled version of XilinxCoreLib.
The project (3 files: my vhdl, the fifo_generator vhdl and the
fifo_gen .edn) compiles just fine, but when I go to simulate in... more »
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Stimulus Counter (from Opto-Sensors)
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Hi,
I am a student of robotics at Plymouth University, England. I have
been using VHDL pretty solidly for about 5 months now and I have come
up against a rather devious problem. The project at hand is using a
small differential drive robot with an Altera Cyclone II FPGA and an
ATmel 64. Using the two active IR sensors on the robot we are to make... more »
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Open file path specification
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In which format the file name should be given? Can it be absolute? When it is relative, it is relative to what? I see that Modelsim has current working dir, whereas Active-HDL looks for files in the project dir, where are the sources. They do not care if file name starts with /root in Windows.... more »
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Sanity check on a weird bit of math and std_logic_unsigned
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Hello folks,
I'm having to do surgery on something a contractor left us. One small problem was that he took a file with numeric_std already defined and used and then for his own additions added std_logic_unsigned (thanks SO much.) Anyhow, I am having to carefully evaluate what he's doing so that I don't unnecessarily break something that is already working. Not especially well commented either, so I'm having to infer intent from the code as well.... more »
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Spartan 6 MPMC - more ports?
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Hi,
I have a Spartan 6 project with 7 IP cores wanting VFBC connections to a memory controller. My problem is the MPMC configuration tool won't seem to let me do that because the MPMC can't be configured to have that many VFBC connections.
I'm trying to build a picture-in-picture device for HDMI (6 inputs, 1 output).... more »
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