Newsgroups: comp.lang.vhdl
From: kcn9 <compgro...@cec-services.com>
Date: Sun, 30 Sep 2012 18:23:56 -0500
Local: Sun, Sep 30 2012 7:23 pm
Subject: RE: converting std_logic_vector to an integer without sign extension
My similar problem is this.
LIBRARY ieee ; VARIABLE nlut_idx : INTEGER ;
SUBTYPE slv_bit IS std_logic ; -- notice slv_bit is in the singular
TYPE test_bits_array IS ARRAY ( 0 TO 8) OF slv_bits ; -- 18 bits = 9 x 2-bits
nlut_idx := to_integer( ( test_bits( 8 DOWNTO 0))) ;
-- The above barfs in ISE 14.2 as:
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