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Message from discussion converting std_logic_vector to an integer without sign extension
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kcn9  
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 More options Sep 30 2012, 7:23 pm
Newsgroups: comp.lang.vhdl
From: kcn9 <compgro...@cec-services.com>
Date: Sun, 30 Sep 2012 18:23:56 -0500
Local: Sun, Sep 30 2012 7:23 pm
Subject: RE: converting std_logic_vector to an integer without sign extension
My similar problem is this.

LIBRARY ieee ;
USE ieee.math_real.ALL ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL ; -- use this above scope of **
USE ieee.std_logic_arith.ALL ; -- **
USE ieee.numeric_bit.ALL ;

VARIABLE nlut_idx : INTEGER ;

SUBTYPE slv_bit IS std_logic ; -- notice slv_bit is in the singular
TYPE slv_bits IS ARRAY ( 0 TO 1) OF slv_bit ; -- notice slv_bits is in the plural

TYPE test_bits_array IS ARRAY ( 0 TO 8) OF slv_bits ; -- 18 bits = 9 x 2-bits
VARIABLE test_bits : test_bits_array ;

nlut_idx := to_integer( ( test_bits( 8 DOWNTO 0))) ;

-- The above barfs in ISE 14.2 as:
--
-- ERROR:HDLCompiler:432 - ...
--          Line 16548: Formal <arg> has no actual or default value.
-- ERROR:HDLCompiler:541 - ...
--          Line 16548: Type integer is not an array type and cannot be indexed.


 
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