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From: KJ <kkjenni...@sbcglobal.net>
Newsgroups: comp.lang.vhdl
Subject: Re: bcd-7segment decoder
Date: Thu, 14 Jun 2012 20:15:05 -0700 (PDT)
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On Thursday, June 14, 2012 8:19:31 PM UTC-4, Arthur Merlo wrote:
> Hi guys, I'm new in VHDL and would be glad if anyone could help me
> with
> my bcd-7segments decoder. I dont know why its not compiling
>=20
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> ENTITY decod_7seg IS
> PORT (
> a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
> HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
> );
> END decod_7seg;
> ARCHITECTURE behaviour OF decod_7seg IS
> BEGIN
>=20
>=20
> HEX0 <=3D "1000000";
> when a=3D"0000"
> else
> HEX0 <=3D "1111001";
> when a=3D"0001"
<snip>
> else
> HEX0 <=3D "0010000";
> when a=3D"1001"
>=20
>=20

The correct form is
HEX0 <=3D "1000000"
when a=3D"0000"=20
else=20
"1111001"
when a=3D"0001"=20
else=20
...

Also, if you're planning on turning this into hardware, you need to end the=
 statement without the final condition like this...

"0000000" when a=3D"1000"=20
else "0010000"; -- when a=3D"1001"

Get rid of the last conditional check.  If you don't you'll be defining som=
ething that gets implemented as a form of latch which in programmable devic=
es is generally a 'no-no'.  Just from a logic perspective, ask yourself wha=
t should be the output if the input does not match any of the expected inpu=
ts?  You have to output something, so choose it.  That is the value to use =
on the final 'else' without any additional 'when a=3D ...' conditions.

Kevin Jennings