vhdl / verilog comparing
Maurice
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
Jonathan Bromley
>I know very well VHDL, and nothing about Verilog. which is better and why?
are you trying to incite a riot?
--
Jonathan Bromley
Mike Treseler
> I know very well VHDL, and nothing about Verilog. which is better and why?
Verilog has more built-in support for printing debug messages.
VHDL has more built-in support for advanced synthesis.
-- Mike Treseler
Maurice
"Jonathan Bromley" <jonathan...@MYCOMPANY.com> wrote in message
news:7i3kk5do8v8ocs7v0...@4ax.com...
Not at all, why??
Simply, I don't know anything about verilog, I would just have an idea about
it, comparing with vhdl
Maurice
Maurice
Mike Treseler
> "Jonathan Bromley" <jonathan...@MYCOMPANY.com> wrote in message
> Not at all, why??
> Simply, I don't know anything about verilog, I would just have an idea about
> it, comparing with vhdl
I am sure that Jonathan intended humor.
If you google this group on vhdl vs verilog
you will find many long and contentious treads.
-- Mike Treseler
Rob Gaddi
VHDL, because you already know it.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Petter Gustad
> VHDL has more built-in support for advanced synthesis.
What do you have in mind here?
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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Mike Treseler
> Mike Treseler <mtre...@gmail.com> writes:
>> VHDL has more built-in support for advanced synthesis.
> What do you have in mind here?
Single process entities using no signals.
http://mysite.verizon.net/miketreseler/
Petter Gustad
> Petter Gustad wrote:
>> Mike Treseler <mtre...@gmail.com> writes:
>>> VHDL has more built-in support for advanced synthesis.
>> What do you have in mind here?
>
> Single process entities using no signals.
Why is single process with no signals more advanced when it comes to
synthesis?
Andy
If you need to do fixed or floating point arithmetic in hardware, VHDL
has it in spades over Verilog. This is just one example of the
inherent language capabilities (and not just syntactical sugar) of
VDHL that verlog lacks.
And as mentioned earlier, if you already know one, it is always better
than the one you don't know, unless you have a massive project ahead
and time to climb the learning curve.
Andy
Mike Treseler
> Why is single process with no signals more advanced when it comes to
> synthesis?
That is certainly a matter of opinion.
Structural vs procedural.
I prefer using variables, functions, and procedures
in a single box instead of modules upon modules.
-- Mike Treseler
Andy
I also prefer the immediate update semantics of variables as opposed
to the postponed updates of signals in processes. "I stored this in
the sig up here, but it still has the old value down here later...".
Using variables often makes it easier to insert/remove clock cycles in
your behavioral description. Two references to the same variable can
be registered or combinatorial values independently. The synthesis
tool will do what it takes to create HW that mimics the clock cycle
behavior of your code, which now reads like SW code, without the
postponed values issues. It also makes more sense when using the
source level debugger.
These may or may not be "advantages" to other users.
Andy
David Bishop
> Hello:
>
> I know very well VHDL, and nothing about Verilog. which is better and why?
I like VHDL mainly because I can do more with it than I can Verilog.
The argument boils down to this:
Verilog was written by a bunch of hardware guys who knew nothing about
software. We beat on it 'till you could do software with it.
VHDL was written by a bunch of software guys who knew nothing about
hardware. We beat on it 'till you could do hardware with it.
Petter Gustad
> Petter Gustad wrote:
>
>> Why is single process with no signals more advanced when it comes to
>> synthesis?
>
> That is certainly a matter of opinion.
I see, so it's more a matter of taste.
Petter Gustad
> I also prefer the immediate update semantics of variables as opposed
> to the postponed updates of signals in processes. "I stored this in
> the sig up here, but it still has the old value down here later...".
Yuck. Synthesizable Ada comes to my mind. I guess I'm a little old
fashioned in this regard.
Petter Gustad
> Verilog was written by a bunch of hardware guys who knew nothing about
> software. We beat on it 'till you could do software with it.
Still I prefer SystemVerilog over VHDL for writing testbenches
using classes, constrained random generation, covergroups, queues,
assertions, and other software constructs.
> VHDL was written by a bunch of software guys who knew nothing about
> hardware. We beat on it 'till you could do hardware with it.
Still I prefer VHDL over Verilog for writing DUT's.
Mike Treseler
>>> Why is single process with no signals more advanced when it comes to
>>> synthesis?
>> That is certainly a matter of opinion.
>
> I see, so it's more a matter of taste.
Yes. Bud Lite vs IPA ;)