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Date: Fri, 2 Nov 2012 07:46:15 -0700 (PDT)
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Subject: Re: SLV reverse bit order
From: Andy <jonesa...@comcast.net>
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On Wednesday, October 31, 2012 4:17:49 PM UTC-5, Jim Lewis wrote:
> Currently the language does not have a reverse operator because no one ha=
s bothered to submit a use case for one. If you have something that this is=
 useful for, you should submit it to the working group. Best Regards, Jim L=
ewis

Rather than adding a new operator to VHDL that adds bloat and impacts tool =
vendors, it would be better to add reverse() functions to the ieee packages=
 for the standard vector types? Note that these packages are governed by th=
e same working group. Until that time, you can write and use your own funct=
ions, with the tools you already have.

VHDL already allows extension through code to cover the need. For a taste o=
f what can be done through "extend VHDL through code", take a look at the f=
ixed- and floating-point packages (now part of the standard), or better yet=
 the new Open Source VHDL Verification Methodology (OSVVM) library. These w=
ere all accomplished without changing the language itself.

Andy