comp.lang.vhdl Google Group

Re: Signal xx cannot be synthesized, bad synchronous description error

2013-05-19T13:46:57Z

After going over this a few times in my head, i think i now understand what to do.

I make a new process with the sole purpose of storing the 2 latest values of SET (with the appropriate CLK), then i can change the rising_edge statement with an if (register(0) = '0' and register(1) = '1') then ...

Re: Signal xx cannot be synthesized, bad synchronous description error

2013-05-19T12:19:48Z

Hi Thomas

Thank you for your response.
I understand what you mean, i didn't realize this wasn't allowed but it is quite logical once you think about it.

Could i perhaps change the rising_edge(SET) statement by: if SET'event and SET='1' then ... or is this also wrong?

Or should i let SET go through a D-flipflop so i can check if SET='1' and Q='0' with Q being the output of the flipflop.

Re: Signal xx cannot be synthesized, bad synchronous description error

2013-05-18T14:38:20Z

This is a combinatorial process, it describes the logic behavior of
pure combinatoric (the style for a statemachine is widely used in old/
bad books, use search function to learn about that issue as fsm style
has nothing to do with your problem and it is not wrong)

combinatorial process don't allow rising edge.

Signal xx cannot be synthesized, bad synchronous description error

2013-05-18T11:44:51Z

I need to make a kind of controller for a school project but i keep getting stuck on the same error. which is:

"ERROR:Xst:827 - "D:/School/VHDL/ServoControlle r/ControllerBeta.vhd" line 132: Signal nextstate cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

Re: Counting number of asserted register bits in VHDL

2013-05-17T16:49:05Z

Kevin, leaving out the ' was an unfortunate typo in my original suggestion.

Unsigned() is a built-in type conversion function from any closely related type to unsigned (a cast). In order for it to work, the argument must be statically determinable to be of a single type that is acceptable for the converion function.

Re: Counting number of asserted register bits in VHDL

2013-05-17T15:59:49Z

Andy: Yes, that does work, with the unsigned cast (using ') instead of the unsigned function. I don't really know the difference, but the cast does work.
-Kevin

Re: Asynchronous With Select and When Else Statements

2013-05-17T03:33:48Z

He means something like this...

A <= 'z' when (foo = 1) else B;

B <= stuff when (other stuff);

BTW, separate has "a rat". I was taught that in elementary school and I
never forgot it.

Rick

Re: Counting number of asserted register bits in VHDL

2013-05-16T23:14:17Z

Kevin,

Did you try to_integer(unsigned'(0 => mod_cmplt(k)))?

I usually use the if statement anyway. Much more readable.

Verilog: "Hold my beer and watch this!"

Andy

Re: Generics, packages, and VHDL-2008

2013-05-16T21:52:27Z

On Thu, 9 May 2013 16:12:35 -0700 (PDT)

Just to follow up on this, Aldec says that version 9.3 should come out in August and fix this issue.

--
Rob Gaddi, Highland Technology -- [link]
Email address domain is currently out of order. See above to fix.

Re: Counting number of asserted register bits in VHDL

2013-05-16T20:51:24Z

Le 16/05/2013 21:42, kevin.neil...@xilinx.com a �crit :

> a slice of a character string? No problem; no conversions required.

That's weak typing's advantage. But it lets you so easily shoot yourself
in the foot...

Nicolas

Re: Counting number of asserted register bits in VHDL

2013-05-16T19:42:52Z

Andy,
Thanks--I wasn't sure if the variable had to be initialized to zero. I don't use variables often.

I elided the type conversion in my code snippet (even though that's where I spend half my VHDL development time). I tried your std_logic->integer conversion above and Synplify didn't seem to be liking it, and I ended up having to do a ridiculous conversion like this:

Re: Asynchronous With Select and When Else Statements

2013-05-16T15:02:43Z

If you are willing to live with the warning, it looks like synthesis built HW that behaves like you want, but without any internal tristate, using equivalent logic (assuming pullup). Simulate the gate level (post-synthesis) netlist to verify.

If you don't want the warning, you will have to describe the behavior you want without using internal tri-state signals.

Re: Asynchronous With Select and When Else Statements

2013-05-16T14:14:08Z

I understand what you were talking about, but I didn't understand how that was going to change anything in my problem.

mdio_proc1 and mdio_proc2 are the I/O bidirectional pins in the top module.
I want mdio_proc1 and mdio_proc2 to behave like mdio_bus when it is selected.

For example:

Re: Asynchronous With Select and When Else Statements

2013-05-16T13:40:50Z

"I would never write Q <= d when rising_edge(clk); I would rather put it in a process and use an if statement etc... "

I don't use the concurrent clocked assignment alot, but for the occasional single register or two, a process is just more code to do the same thing with no benefit. The concurrent assignment is slightly less efficient in simulation, but for a single register here and there, the impact is nil.

Re: Asynchronous With Select and When Else Statements

2013-05-15T19:23:04Z

Yeah when I meant Asynchronous I meant not using a clock. I would never write Q <= d when rising_edge(clk); I would rather put it in a process and use an if statement etc...

Could you give me an example of what you mean by Break up the assignments into a seperate with-select assignment for the data, followed by a when-else assignment for the tri-state buffer.

Re: Counting number of asserted register bits in VHDL

2013-05-15T17:58:14Z

Thanks, Andy. I'm new to VHDL. It took me most of the morning to figure out how to add a std_logic bit to an integer (to_integer). You make some very good points in the rest of your post as well.

Re: Asynchronous With Select and When Else Statements

2013-05-15T16:11:05Z

You need to break up the assignments into a separate with-select assignment for the data, followed by a when-else assignment for the tri-state buffer.

You might try to see if XST has a "tri-state push" option, but I doubt it will work for your code anyway.

BTW, the statements you are using are not called "asynchronous" (a function of the logic expressed), but are called "concurrent" (a function of when the statement is executed). Concurrent assignment statements can infer synchronous registers, as in the following:

Re: Counting number of asserted register bits in VHDL

2013-05-15T15:47:16Z

A nice little problem to illustrate VHDL RTL...

I don't know if it makes a real difference, but constraining the range of sum is seldom a bad idea:

variable sum : natural range 0 to mod_cmplt'length;

Don't forget to initialize sum to 0 before the loop, on every clock cycle. Variable declaration initializations in processes only happen once, at time 0.

Asynchronous With Select and When Else Statements

2013-05-15T14:50:02Z

Hi everyone,

I am coding up a project to route and control Gigabit ethernet.

Basically the FPGA receives MDIO communication from Processor 1 or Processor 2( Both masters, only one can be master at a time).

The logic decides based on a priority and a keep alive signal which master controls the MDIO bus.

Re: Counting number of asserted register bits in VHDL

2013-05-15T14:21:34Z

> if only 8 modx modules were instantiated. Even though the if-else
branch for
> 16 modx's wouldn't be reached, the adder would still have inputs for
modx[8]
> to modx[15] which would not be driven.

Actually the adder would not have extra undriven inputs _because_ those
branches are not reached, and the synthesizer only implements code that

Re: Counting number of asserted register bits in VHDL

2013-05-15T11:49:02Z

Thank you - this looks interesting. So sum gets evaluated at clk'event in time for cmplt_cnt to be updated with the new value of sum?

Re: Counting number of asserted register bits in VHDL

2013-05-15T11:39:36Z

Thank you. I thought about this but didn't know what would happen to the adder if only 8 modx modules were instantiated. Even though the if-else branch for 16 modx's wouldn't be reached, the adder would still have inputs for modx[8]to modx[15] which would not be driven.
Also, you are correct, generate statements may not be located in a process.

Re: Counting number of asserted register bits in VHDL

2013-05-14T23:05:00Z

Yeah, it seems like something much simpler like this would work fine:

process (reset, clk)
variable sum : integer := 0;
begin
if (reset = '1') then
cmplt_cnt <= 0;
elsif (clk'event and clk='1')
for k in 0 to R_SIZE - 1 loop
sum := sum + mod_cmplt(k);

Re: Counting number of asserted register bits in VHDL

2013-05-14T20:52:31Z

I'm not up enough on VHDL to tell you if it's even valid
to have generate statements within a process, but the point is
that you don't need them here. Since mod_cmplt is always the
same size regardless of the value of R_SIZE, you can just use
if ... elsif ... else without the generates. Or even use a case

Counting number of asserted register bits in VHDL

2013-05-14T20:30:27Z

Hello,

I have a status register of width, R_SIZE. This is a generic so the register width may be different depending on the application. The R_SIZE is limited to values, 4, 8 and 16.

Each bit in the register is set by different module as an indication of that module's done status. These status bits are asserted for only one clock and may be asserted again as each module may run its application multiple times on different data.

Re: i need solutions of chapter 5 wireless communication by Andrea Goldsmith

2013-05-14T03:07:44Z

Yes. So do I. Can you share them to me? Thank you so much. My email : Mrdungd...@gmail.com

Re: clocked process and sensitivity list

2013-05-13T12:53:28Z

Rick,

We are in complete agreement, but saying the same thing in different ways.

The feedback mux IS A CLOCK ENABLE. If the target architecture supports built-in clock enables on registers, then one will be used to implement the feedback mux.

It may be that at the time during processing when the need for a feedback mux is determined, it may not be known whether the target architecture supports built-in clock enables, thus the message indicates a feedback mux.

Re: clocked process and sensitivity list

2013-05-10T15:04:16Z

I'm not sure that is really needed. If the reset clause is missing an
assignment doesn't it become a clock enable? When the reset is asserted
the clock does not work and the output is held. Still no need for a
feedback mux...

Rick

Re: clocked process and sensitivity list

2013-05-10T13:33:05Z

I've found that Symplify is very good at warning you about
forgetting the reset terms in this case. You get a warning
about feedback mux, followed by "Did you forget..."

I wish XST did that instead of all the useless warnings it
gives...

--
Gabor

Re: clocked process and sensitivity list

2013-05-10T09:45:56Z

The feedback mux is needed if you *forget* to reset the register
in the 'if reset' clause. In that case, HDL semantics dictate
that the register should keep its previous value during reset,
hence the feedback mux.

Jan

--
Jan Decaluwe - Resources bvba - [link]
Python as a HDL: [link]

Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs

2013-05-10T06:18:09Z

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Re: clocked process and sensitivity list

2013-05-10T04:48:31Z

That's what I'm not clear on. I don't see why *anything* is needed to
keep the register in reset as long as the reset is asserted. That's
what the reset does, it holds the FF in reset. I've never seen a
feedback mux added to a FF to implement a reset. Or are you referring
to the internal logic of the FF?

Re: Generics, packages, and VHDL-2008

2013-05-09T23:12:35Z

I think the large number of changes in 2008, combined with poor user-knowledge of the new features, and therefore little input from customers clamoring for them, all contributed to the delay in implementing these changes.

Regardless of whether you find/use a work-around, let them know you need this feature. It helps them prioritize their efforts.

Re: Generics, packages, and VHDL-2008

2013-05-09T20:59:59Z

On Thu, 9 May 2013 13:35:04 -0700

Found a workaround, at least for the special case of this issue. I was
under the impression for some reason that you couldn't take a pointer
to an incomplete type, and so I needed to make
subtype t_element is std_logic_vector(DATA_WIDTH-1 downto 0);

if I wanted to do dynamic structures with it.

Re: Generics, packages, and VHDL-2008

2013-05-09T20:35:04Z

On Thu, 9 May 2013 13:17:41 -0700 (PDT)

Thanks, Andy.

I added the following line into the architecture declaration:

package ldq is new data_queue
generic map (
DATA_WIDTH => DATA_WIDTH
);

But during compilation I got the message:
Local instantiation of packages is not supported yet. Please contact

Re: Generics, packages, and VHDL-2008

2013-05-09T20:17:41Z

Rob,

You can put a Package Instantiation Declaration in the declarative region of the entity, architecture, block, or several other declarative regions (not process).

If the generic you wish to use is visible where the PID is, then that generic can be used in the PID's generic map aspect.

You can include a use statement after the PID to access declarations within it.

Re: VHDL Standards Invitation and Status

2013-05-09T19:45:24Z

Rather than allow the reverse range to be used as an index range, I would prefer a standard function(s), such as right_to_left() to return a bit-reversed vector (with reversed range to match.)

Such a fix would have far less impact on tool vendors (and therefore adoption/support) than directly allowing reversed range access of vectors.

Generics, packages, and VHDL-2008

2013-05-09T19:16:09Z

Hey y'all --

If I have an entity with a generic, call it DATA_WIDTH. And I want
that entity to use a package that has a DATA_WIDTH generic, in this
specific case the package provides for a queue, implemented on shared
variables, that the package would use.

Is there any way to call out the instantiated package using the

Re: verification strategy with no specs

2013-05-09T19:13:44Z

I agree, without a specification, you cannot verify function.

However, there are established design standards, regardless of function, that are prescribed to avoid certain, most often unintended, consequences and hazards.

The design can be reviewed per those standards with little or no knowledge of what the circuit is supposed to do.

Re: clocked process and sensitivity list

2013-05-09T18:55:39Z

Rick,

In the typical pattern for clocked logic with asynchronous reset:

if reset then
-- asynchronous reset/preset assignments to registers
eslif rising_edge(clk) then
-- synchronous assignments to registers
end if;

The elsif keeps the synchronous section from executing while reset is active.

Re: VHDL Standards Invitation and Status

2013-05-09T18:45:39Z

I didn't look very deep into the existing requests, but I wonder if
anyone considered bit reversal, for example allowing SLV's defined
as (N downto 0) to be referenced in reverse order (0 to N).

PRO:
Reduces use of loops for intentional bit reversal

CON:
Could happen unintentionally when you thought you had a

VHDL Standards Invitation and Status

2013-05-09T18:16:57Z

Hi,
The VHDL Standards group is currently working on VHDL 1076-201X.
Currently we are working on developing language change proposals.
Check them out at:
[link]

Did we miss something? Could the proposals be better?

Join us and help out. We have many tasks that can involve

Re: verification strategy with no specs

2013-05-08T20:42:27Z

Hi John,

[]
[]

I wish I had the kind of beard to allow me such a statement!

So your suggestion is to sit down with the current designer(s) and try
to get an higher level description of the various components in order to
define interfaces, functionality and performances.

Maybe I should size the effort and come with a proposal to the group in

Re: verification strategy with no specs

2013-05-08T16:50:47Z

Here's what you do: Get an audience, scratch your head and rub your
beard while looking pensive. Then declare with authority "It appears
the product meets all stated specifications".

Seriously, you'll need to write the specs before you can test it. It
sounds like that's what you're doing anyway. I sympathize with you. It

verification strategy with no specs

2013-05-08T09:13:40Z

Dear all,

I've been appointed to review and verify a vhdl project of about 25k
lines of code, *without* a specification document!

There are various scattered notes/docs which describes somehow some
details (*not all*), but there's no description of what the individual
parts should do, even though there are only 4 types of FPGA in the system.

Re: clocked process and sensitivity list

2013-05-08T05:30:18Z

Hi alb!

This is correct for simulation. Most synthesis tools don't care for the
sensitivity list and "generate their depending on the code".

It depends on the target library, because it has to include flipflops
with async. set and reset. An for these flipflops in the synthesis model

Re: clocked process and sensitivity list

2013-05-07T18:27:40Z

I'm not following the issue here. I can't see why any extra logic would
need to be asserted. The clocked process infers a register for each bit
assigned in the edge triggered section. Are the async assigned bits
*not* assigned in the edge triggered section?

What am I missing?

Re: clocked process and sensitivity list

2013-05-07T13:27:48Z

Alb,

My use of "almost always" instead of "always" is just being cautious. I have never had a case where it was not caused by a missing assignment in a process with a preceding asynchronous reset clause. But I have not written every possible combination of code yet, nor have I used every synthesis tool.

Re: clocked process and sensitivity list

2013-05-07T08:55:41Z

Hi Ralf,

Uhm, I guess you are right. Indeed I guess I was also right that
'foobar' is scheduled for a change in the next delta cycle, but if the
process is not sensitive to it (with the sensitivity list) than it will
not trigger. Is this a correct statement?

Well, I've raised this question also. Indeed I did not even receive a

Re: clocked process and sensitivity list

2013-05-07T08:34:57Z

Hi Andy,

I believe that 'almost' in your statement is referred to the variability
of the various synthesis tools' implementation.

meaning that if a signal is not set for *all* sets and resets, the
synthesis needs to 'remember' the state of the not-assigned signal to
maintain its state. Sorry if I needed to reformulate it, but I guess is