Delays on bidirectional signals
Frederic Freck
My appologies if this is my second posting. I tried to post
this question once before, but I don't think it made it to
the newsgroup.
I have a design which has two components. Each component
has a bidirectional (inout) port. I'll call them A and B.
I need to connect A to B, and I need to simulate the
wire delay between A and B. Assume that I cannot see into
the components, and thus, do not know when A or B is really
driving. Is there a way to simulate the delay?
If I do the following:
A <= B after 5 ns;
B <= A after 5 ns;
I get caught in the loop of A causing an event on B,
and B causing an event on A and I get X's everywhere
(I'm using std_logic signals).
Does anyone have any ideas?
Thanks!
Donna
VhdlCohen
In article <33F3E2...@worldnet.att.net>, Frederic Freck
<fr...@worldnet.att.net> writes:
>I have a design which has two components. Each component
>has a bidirectional (inout) port. I'll call them A and B.
>I need to connect A to B, and I need to simulate the
>wire delay between A and B. Assume that I cannot see into
>the components, and thus, do not know when A or B is really
>driving. Is there a way to simulate the delay?
>
>If I do the following:
>
>A <= B after 5 ns;
>B <= A after 5 ns;
>
>I get caught in the loop of A causing an event on B,
>and B causing an event on A and I get X's everywhere
>(I'm using std_logic signals).
>
>Does anyone have any ideas?
Below is a reply I received on the subject. I haven't tested it. But
it is a variation to my
model.
Another solution to this wire emulation that does not have these
restrictions is to use
mixed mode simulation with Verilog. One needs to build a Verilog module
with the tran bidirectional pass gate primitive. In mixed mode simulation,
it is possible to use this module with VHDL.
I haven't had the time to work this solution out yet. If someone wants to
volunteer it, that would be great!.
Ben Cohen
-----------------------
Re[2]: Help! Wire Delay Model needed.
Date: 97-07-22 15:20:06 EDT
From: Albert...@ccm.co.intel.com (AlbertX Cheng)
To: Vhdl...@AOL.COM
Text item:
Ben,
Thanks for you help. Your model is better than mine due to the fact
that your model recovers from an X correctly (e.g A->1 B->0 ==> A &
B->X, then A->Z ==> A & B->0). The attached file is an alteration of
yours that includes wire delays. The flaw of this new version is that
any transactions occur before the two terminals settle down will be
ignored.
Thanks again for your help. Two books published, that's pretty good.
Albert Cheng
albert...@ccm.co.intel.com
______________________________ Reply Separator
_________________________________
Subject: Re: Help! Wire Delay Model needed.
Author: Vhdl...@aol.com at SMTPGATE
Date: 7/22/97 10:15 AM
In article <33CBB89C...@ccm.co.intel.com>, Albert Cheng
<albert...@ccm.co.intel.com> writes:
> I am trying to write a bus-loss wire delay model. It is simply a
> bi-directional delay line. It has two terminals (A and B), when an
>
> assignment is made to A, it will propagate to B after a certain
>amount
> of time (passed in by using a generic). Same thing happens when an
>
> assigment is made to B, it propagates to A. The following method
> doesn't quite work:
>
> process (a)
> if (not(b = a) then
> b <= a after delay;
> end if;
> end process;
>
> process (b)
> if (not(a = b) then
> a <= b after delay;
> end if;
> end process;
>
> The model above works as long as it doesn't go to x. If A is 1 and
>B is 0,
> both terminals will go to X and does not recover correctly. An
>almost
> good method is to reduce the strength when propagating through,
>like
> 1->H or 0->L etc. But that's not quite the same. Especially when
> either A or B is tied to a pullup (H) or pulldown (L), it will go
>to X. Any ideas?
>
>
Take a look at my zero ohm resistor model at my web site.
It implements a bidirectional wire. The problem you have is with the
dirvers.
You need to implement a break before make (i.e. assign a 'Z' to A and B, and
then
make the transfer assignment). This is where Verilog beats VHDL because
they implement
a transfer gate. I am requesting that VHDL'98 implements a transfer gate.
--=============================================
-- Ben Cohen, Hughes Aircraft Co, RE- R1/B507
-- ** "VHDL Coding Styles and Methodologies",
-- ISBN 0-7923-9598-0 Kluwer Academic Publishers, 1995.
-- ** "VHDL Answers to Frequently Asked Questions"
-- ISBN 0-7923-9791-6 Kluwer Academic Publishers, 1997.
-- FTP site: users.aol.com /vhdlcohen/vhdl
-- Web page: http://members.aol.com/vhdlcohen/vhdl
-- (310) 334-7389, fax: (310) 334-1749
--=============================================
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm0_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- Vhdl...@aol.com
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm is
generic(a_to_b_loss : time := 1 ns;
b_to_a_loss : time := 2 ns);
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm;
architecture ZeroOhm_a of ZeroOhm is
begin
ABC0_Lbl: process
variable ThenTime_v : time := 0 ns;
function max(t1,t2 : time) return time is
begin
if (t1 > t2) then
return t1;
else
return t2;
end if;
end;
begin
wait on A'transaction, B'transaction
until ThenTime_v + max(a_to_b_loss, b_to_a_loss) < now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= transport B after b_to_a_loss;
B <= transport A after a_to_b_loss;
end process ABC0_Lbl;
end ZeroOhm_a;
--=============================================
-- Ben Cohen, Hughes Aircraft Co, RE- R1/B507
-- ** "VHDL Coding Styles and Methodologies",
-- ISBN 0-7923-9598-0 Kluwer Academic Publishers, 1995.
-- ** "VHDL Answers to Frequently Asked Questions"
-- ISBN 0-7923-9791-6 Kluwer Academic Publishers, 1996.
-- FTP site: users.aol.com /vhdlcohen/vhdl
-- Web page: http://members.aol.com/vhdlcohen/vhdl
-- (310) 334-7389, fax: (310) 334-1749
--=============================================