Verilog/VHDL Comparison List
VhdlCohen
because
he had to give a presentation and wanted to be prepared for such a
question. I prepared the
following comparion which I thought might be of interest to others.
--------------------------------------------------------------------------
-----------------
The book "VHDL Designer's Reference", Jean-Michel Berge,
Kluwer Academic Publishers 1992, ISBN 0-7923-1756-4, does good job
in comparing Verilog to VHDL (see pages 231-317).
A possible answer to an audience about a comparison between the
languages can go something like this:
1. Verilog and VHDL share common characteristics (clear separation
between concurrent and sequential domain, concurrent semantic
(delta time), and software constructs (subprograms).
2. VERILOG has more predefined operators, predefined gates, predefined
resolution functions. Verilog includes the don't care notion.
Verilog seems better for IC designs.
3. VERILOG can be used to model devices at lower level than VHDL
(e.g switch level).
4. VERILOG includes convenient truth table syntax to model
primitives. However, the VITAL packages now provide this feature.
5. VHDL includes more constructs for high-level modeling (abstract
data types, packages, ..). VHDL is more appropriate for
system level modeling.
6. VERILOG Features which Surpass VHDL ("The VERILOG Good")
. Clearer distinction between a REGISTER and nets. Nets are
used to model electrical connections. Registers hold
values, acting as memory element.
. Nets have strengths and delay properties which emphasize
their physiscal aspects. The delay may consist of up
to 9 values: a defferent value may be given for each transisiton
to 0, 1, Z and for each minimum, typical, and maximum case.
Such a delay attached to a net is added to the delay of
each assigned statement. The net types include wire or tri,
wand or triand, wor or trior, tri0, tri1 (resistive), supply0,
supply1, trireg (with charge storage).
. Primitive gates include the and, or, xor gate.
7. VERILOG Features which are Inferior to VHDL ("The VERILOG Ugly")
. No concept of Package in Verilog. Functions and procedures
used within a module have to be defined inside the same module,
thus, they cannot be shared by different modules. In Verilog,
a fictitious module with functions and procedures could be
declared and instantiated to emulate the package concept.
Verilog does not have a library management, and does not support
separate compilation. In Verilog, all modules used in the
same simulation must be written in the same file.
. Verilog types are very restrictive and specific to IC modeling
(wire,..supply1).
9. Other Considerations
. Readability
- VHDL is more readable with roots from Ada.
- Verilog is more C like, and may be preferred by C programmers.
- Not all operators are inlcuded in both languages
(e.g. unary reduce in Verilog, mod in VHDL).
. Verilog does not have the concurent procedure statement.
Bottom line: For ASIC designs, Verilog more closely defines the
hardware. For higher level model,
Verilog appears very limitied because of the lack of
packages and minimal type definitions (records, access,
enumeration).
--=============================================
-- Ben Cohen, "VHDL Coding Styles and Methodologies ",
-- ISBN 0-7923-9598-0 Kluwer Academic Publishers.
-- Hughes Aircraft Co, RE- R1/B507
-- 2000 East Imperial Hwy
-- El Segundo, Ca, 90245
-- (310) 334-7389, fax: (310) 334-1749
--=============================================
Peet James (peetj)
: 7. VERILOG Features which are Inferior to VHDL ("The VERILOG Ugly")
: . No concept of Package in Verilog. Functions and procedures
: used within a module have to be defined inside the same module,
: thus, they cannot be shared by different modules. In Verilog,
: a fictitious module with functions and procedures could be
: declared and instantiated to emulate the package concept.
: Verilog does not have a library management, and does not support
: separate compilation. In Verilog, all modules used in the
: same simulation must be written in the same file.
: . Verilog types are very restrictive and specific to IC modeling
: (wire,..supply1).
I would add:
7b. Verilog Ugly: Verilog developed from the bottom up. Thus many
'repairs' and additions have been made along the way. These are
usually done in the PLI or via compiler directives. It is very
easy to back yourself into a corner on large designs or in large
companies. Becoming dependent on PLI routines, or compiler directive
fixes. Bottomline is that your code becomes non-transportable
between simulators or even between versions of the same simulator.
This can happen with all programming languages unless a good process,
a good testcase structure, and overall script methodology is devel-
oped and used. VHDL tends to lend itself to this more. Verilog
has been more piecemeal in its developement, and has not lent itself
to smooth transitions.
erik jessen
- Verilog: is not a standard; I was told by a manager at Logic Modelling that
they have found that the Verilog "standard" is such, that the same
code will generate different sim results on different simulators,
and both simulators will meet the standard. This means that
Verilog is not portable. This should definitely be a consideration
at large companies, for maintainability reasons. LMC said in
comparison that if the VHDL code compiled, it would give the same
results on every simulator. Verilog doesn't have a timing wheel
in its definition, I'm told, and this is the reason for the problem.
- Verilog: people I know who have learned Verilog (including myself) have
found it frustrating because half the syntax structures are C, and
half are Ada, and we could never remember which one we were supposed
to use in a particular case.
- Figure that at least 50% of your design cycle is spent doing testbenches
and sim. A large part of that is system-sim, where VHDL is MUCH
better. Generics and configuration statements make documenting
and rerunning sims much more clean than with Verilog. Chip designs
aren't getting any smaller, and this should be a big consideration.
These are some practical aspects that have come up, as I've designed Verilog
and VHDL chips.
Erik Jessen
Engineering Director
Com-Solutions
Jan Decaluwe
> 6. VERILOG Features which Surpass VHDL ("The VERILOG Good")
> . Clearer distinction between a REGISTER and nets. Nets are
> used to model electrical connections. Registers hold
> values, acting as memory element.
The relation of a hardware register with a Verilog reg is,
I believe, at least as vague as with VHDL signals / variables.
To get a HW register, you need a reg, but whether a reg
actually becomes a HW register depends on how it is used in the code.
Verilog reg's behave similarly to VHDL (shared) variables when "normal"
assignment is used, and to VHDL signals when non-blocking assignment
is used. By looking at it that way, the rules that define whether or
not you'll get a HW register (after RTL synthesis) become similar in both
languages.
There are many languages that *do* make a clear distinction between
HW registers and nets, in contrast to Verilog & VHDL. UDL/I is an example.
If this would really be a crucial advantage, we would probably all be
designing in such a language instead of in Verilog or VHDL.
The problem with languages like UDL/I is that they typically also lack
support for procedural (sequential) descriptions. I believe that both
characteristics are related: the "ambiguity" of procedural variables is
avoided by simply not supporting them. Using such a language basically means
that you'd have to describe everything using concurrent statements only.
Pretty hopeless, if you ask me.
Regards, Jan
--
===================================================================
Jan Decaluwe === Easics ===
Design Manager === VHDL-based ASIC design services ===
E-mail: ja...@easics.be ===================================
Tel: +32-16-270 400
Fax: +32-16-270 319 Kapeldreef 60, B-3001 Leuven, BELGIUM
Janick Bergeron
Rich Abato <rab...@jolt.agile.com> wrote:
>>>In article <417fsl$h...@newsbf02.news.aol.com> vhdl...@aol.com (VhdlCohen) writes:
>>> 2. VERILOG has more predefined operators, predefined gates, predefined
>>> resolution functions. Verilog includes the don't care notion.
>>> Verilog seems better for IC designs.
1164 does not handle the '-' properly and lack the arithmetic operations
which are to be provided by NUMERIC_BIT and NUMERIC_STD.
>>> 3. VERILOG can be used to model devices at lower level than VHDL
>>> (e.g switch level).
> I can't think of a single reason this can't be done in VHDL.
One reason: performance. Just like VHDL without VITAL is useless for
gate-level modeling, VHDL without a set of switch-level primitives
is useless. Not becasue it can't but because it is not practical in
terms of performance, ease of modelling and model maintainability.
> VHDL also has generics which make library modeling much
> easier! Synthesis makes these high level constructs
> very useful in chip design also.
Verilog as parameters which act like generics. They are also supported
by synthesis.
>>> In Verilog, all modules used in the
>>> same simulation must be written in the same file.
False.
> Verilog has no concept of configurations.
Configuration can be emulated by using the '-f' option on the command line.
Because Verilog lacks the separate implementation/interface concept, one
cannot instantiate different models of the same module in teh same
simulation.
> Verilog has no generics / generate statements.
See above. The new iterated instances provides a for-generate-like
construct, The preprocessor provides an if-generate-like constructs
(albeit less powerful)
> Verilog has no textio.
True but mostly false. The test output of Verilog is MUCH easier to use
since it has a printf() like statement, but its test input is much poorer
being limited to loading bin/hex image files into memories.
>>> 9. Other Considerations
>>> . Readability
>>> - VHDL is more readable with roots from Ada.
>>> - Verilog is more C like, and may be preferred by C programmers.
I can write obfuscated code in either language liek the best of them.
Writing readable models is more a matter of style and experience than
the language itself.
>Bottom line:
> Anything that can be done in Verilog can also be
>done in VHDL. The reverse is not true.
With proper creativity, the reverse can be done for any VHDL model.
For RTL models, both languages are 100% equivalent.
The choice of HDL will be dictated by business issues, not the languages
by and of themselves.
For those of you who wish to learn more about Verilog, I've was asked
to present my tutorial "Verilog for Experienced VHDL Users" again at the
next VIUF.
--
Janick Bergeron Qualis Design Corporation Ph.: (503) 531-0377
Director of PO Box 4444 Fax: (503) 629-5525
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training
--
Janick Bergeron Qualis Design Corporation Ph.: (503) 531-0377
Director of PO Box 4444 Fax: (503) 629-5525
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training
Rich Abato
I can't agree with many points, sorry for the long repost.
>>In article <417fsl$h...@newsbf02.news.aol.com> vhdl...@aol.com (VhdlCohen) writes:
>>
>> I was asked by a manager to provide a comparison between Verilog/VHDL
>> because
>> he had to give a presentation and wanted to be prepared for such a
>> question. I prepared the
>> following comparion which I thought might be of interest to others.
>> --------------------------------------------------------------------------
>> -----------------
>> The book "VHDL Designer's Reference", Jean-Michel Berge,
>> Kluwer Academic Publishers 1992, ISBN 0-7923-1756-4, does good job
>> in comparing Verilog to VHDL (see pages 231-317).
>> A possible answer to an audience about a comparison between the
>> languages can go something like this:
>>
>> 1. Verilog and VHDL share common characteristics (clear separation
>> between concurrent and sequential domain, concurrent semantic
>> (delta time), and software constructs (subprograms).
VHDL also has configurations an important concept.
>> 2. VERILOG has more predefined operators, predefined gates, predefined
>> resolution functions. Verilog includes the don't care notion.
>> Verilog seems better for IC designs.
Most of this is also supported but the IEEE 1164 package.
>> 3. VERILOG can be used to model devices at lower level than VHDL
>> (e.g switch level).
I can't think of a single reason this can't be done in VHDL.
>> 4. VERILOG includes convenient truth table syntax to model
>> primitives. However, the VITAL packages now provide this feature.
True.
>> 5. VHDL includes more constructs for high-level modeling (abstract
>> data types, packages, ..). VHDL is more appropriate for
>> system level modeling.
VHDL also has generics which make library modeling much
easier! Synthesis makes these high level constructs
very useful in chip design also.
>> 6. VERILOG Features which Surpass VHDL ("The VERILOG Good")
>> . Clearer distinction between a REGISTER and nets. Nets are
>> used to model electrical connections. Registers hold
>> values, acting as memory element.
>> . Nets have strengths and delay properties which emphasize
>> their physiscal aspects. The delay may consist of up
>> to 9 values: a defferent value may be given for each transisiton
>> to 0, 1, Z and for each minimum, typical, and maximum case.
>> Such a delay attached to a net is added to the delay of
>> each assigned statement. The net types include wire or tri,
>> wand or triand, wor or trior, tri0, tri1 (resistive), supply0,
>> supply1, trireg (with charge storage).
>> . Primitive gates include the and, or, xor gate.
>> 7. VERILOG Features which are Inferior to VHDL ("The VERILOG Ugly")
>> . No concept of Package in Verilog. Functions and procedures
>> used within a module have to be defined inside the same module,
>> thus, they cannot be shared by different modules. In Verilog,
>> a fictitious module with functions and procedures could be
>> declared and instantiated to emulate the package concept.
>> Verilog does not have a library management, and does not support
>> separate compilation. In Verilog, all modules used in the
>> same simulation must be written in the same file.
>>
>> . Verilog types are very restrictive and specific to IC modeling
>> (wire,..supply1).
ADD:
Verilog has no concept of configurations.
Verilog has no generics / generate statements.
Verilog has no textio.
Verilog is not strongly typed (It will be happy
to allow you to connect a 32 bit bus with an
8 bit bus and just pad the missing bits).
Verilog has no access types
>> 9. Other Considerations
>> . Readability
>> - VHDL is more readable with roots from Ada.
>> - Verilog is more C like, and may be preferred by C programmers.
(I am a C programmer and I prefer VHDL)
>> - Not all operators are inlcuded in both languages
>> (e.g. unary reduce in Verilog, mod in VHDL).
>> . Verilog does not have the concurent procedure statement.
>> Bottom line: For ASIC designs, Verilog more closely defines the
>> hardware. For higher level model,
>> Verilog appears very limitied because of the lack of
>> packages and minimal type definitions (records, access,
>> enumeration).
>> --=============================================
>> -- Ben Cohen, "VHDL Coding Styles and Methodologies ",
>> -- ISBN 0-7923-9598-0 Kluwer Academic Publishers.
>> -- Hughes Aircraft Co, RE- R1/B507
>> -- 2000 East Imperial Hwy
>> -- El Segundo, Ca, 90245
>> -- (310) 334-7389, fax: (310) 334-1749
>> --=============================================
Bottom line:
Anything that can be done in Verilog can also be
done in VHDL. The reverse is not true. The only
valid arguments for using Verilog are:
1) You have a group of designers who already
know Verilog but not VHDL.
2) You already own the Verilog tools.
--
Richard P. Abato rab...@agile.com (508) 263-3600 x132
Agile Networks, Inc. 1300 Massachusetts Avenue Boxborough, MA 01719
~~~~~~~~~~~~~~~~~~~~~~~ http://www.agile.com ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Robert Brashears
>In article <RABATO.95A...@jolt.agile.com>,
>Rich Abato <rab...@jolt.agile.com> wrote:
>>>> In Verilog, all modules used in the
>>>> same simulation must be written in the same file.
>
>> Verilog has no concept of configurations.
>Because Verilog lacks the separate implementation/interface concept, one
>cannot instantiate different models of the same module in teh same
>simulation.
It is possible to instantiate the same module twice with different
implementations. There are a couple ways to do it I can think of but
all of them are quite a bit messier than the VHDL method. Probably
the cleanest is to use `uselib to specify the implementation by
specifying the source library with the module definition/implentation
wanted before each instantiation. The old way was to use the library
scanning order options. This was really only useful in very simple
scenarios such as simulation two asics together where each had a
different library but some cells in the different libraries had
overlapping names. This was not a useful method for the general
case.
--Robert
Janick Bergeron
Robert Brashears <rob...@cadence.com> wrote:
>It is possible to instantiate the same module twice with different
>implementations. There are a couple ways to do it I can think of but
>all of them are quite a bit messier than the VHDL method. Probably
>the cleanest is to use `uselib to specify the implementation by
>specifying the source library with the module definition/implentation
>wanted before each instantiation.
the Verilog standard. Furthermore, it is only applicable to "library"
cells loaded using the '-y' option. There is no way to load different
implementations of arbitrary modules and their sub-modules.