<OT?> nonstandard use

[churchy]

Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard
"semi-analog" manner? Doing things like using a gate as a comparator etc.

For example, can leftover gates in a device be used to clock the device
with something like the classic 2 not, 2 resistor & a cap oscillator?

CPLDs are nominally still gates but it seem like FPGA might get a little
weird with this though basically externally both ae supposed to look like
simple logic.

3ch

[Andreas Ehliar]

On 2011-09-21, churchy <r...@cox.net> wrote:
> Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard
> "semi-analog" manner? Doing things like using a gate as a comparator etc.
>

I wouldn't recommend it, but you can certainly do something like this. You
can certainly implement something like a ring oscillator in an FPGA if you
felt like it.

One of the neatest ways to abuse an FPGA to do analog processin that I've seen
can be seen on bunnie's blog at http://www.bunniestudios.com/wordpress/?page_id=22
and http://www.bunniestudios.com/blog/?page_id=24 (a way to create a DAC using
just an FPGA and some resistors).

And another favourite: http://www.informatics.sussex.ac.uk/users/adrianth/cacm99/node3.html
http://www.informatics.sussex.ac.uk/users/adrianth/ascot/paper/paper.html


/Andreas

[Jezmo]

It is possible with CPLDs and I have done it myself, I doubt that it
would work with FPGAs due to the complex nature of the output drivers.