Is it really true that there is no simple way to reverse the bit order of a SLV ?
so I need to code a " for ... loop" or make a function with all that ???
I want:
a_rev(ASIZE-1 downto 0) <= a(0 to ASIZE-1);
--this would work if VHDL compilers were not so nose up ;-)
--but seems we were born to suffer :-(
> Is it really true that there is no simple way to reverse the bit order
> of a SLV ?
> so I need to code a " for ... loop" or make a function with all that ???
> I want:
> a_rev(ASIZE-1 downto 0) <= a(0 to ASIZE-1);
> --this would work if VHDL compilers were not so nose up ;-)
> --but seems we were born to suffer :-(
> Any ideas ?
> Thanks
> Luis C.
What happens when you try the code above? I would expect this to work.
> On 10/16/2012 8:22 PM, Luis Cupido wrote:
>> Hello,
>> Is it really true that there is no simple way to reverse the bit order
>> of a SLV ?
>> so I need to code a " for ... loop" or make a function with all that ???
>> I want:
>> a_rev(ASIZE-1 downto 0) <= a(0 to ASIZE-1);
>> --this would work if VHDL compilers were not so nose up ;-)
>> --but seems we were born to suffer :-(
>> Any ideas ?
>> Thanks
>> Luis C.
> What happens when you try the code above? I would expect this to work.
> Rick
Unfortunately I get this:
Error (10484): VHDL error at f_address.vhd(198): range direction of object slice must be same as range direction of object
so this is because I have "signal a: std_logic_vector(ASIZE-1 downto 0);"
if i put it " 0 to ASIZE-1" I keep the compiler happy
but bits will not be reversed !!!!
On 17 ΟΛΤ, 04:22, Luis Cupido <cup...@ua.pt> wrote:
> Is it really true that there is no simple way to reverse the bit order
> of a SLV ?
> so I need to code a " for ... loop" or make a function with all that ???
Here is my function I use very long time:
function Reverse (x : std_logic_vector) return std_logic_vector is
alias alx : std_logic_vector (x'length - 1 downto 0) is x;
variable y : std_logic_vector (alx'range);
begin
for i in alx'range loop
y(i) := alx (alx'left - i);
end loop;
> On 17 ΟΛΤ, 04:22, Luis Cupido<cup...@ua.pt> wrote:
>> Is it really true that there is no simple way to reverse the bit order
>> of a SLV ?
>> so I need to code a " for ... loop" or make a function with all that ???
> Here is my function I use very long time:
> function Reverse (x : std_logic_vector) return std_logic_vector is
> alias alx : std_logic_vector (x'length - 1 downto 0) is x;
> variable y : std_logic_vector (alx'range);
> begin
> for i in alx'range loop
> y(i) := alx (alx'left - i);
> end loop;
> return y;
> end;
Andrew,
Excellent. Thanks.
I see there is no easy/built-in way
but the function you just gave fits just perfect.
> On 10/17/2012 6:26 AM, andrew_b wrote:
>> On 17 ΟΛΤ, 04:22, Luis Cupido<cup...@ua.pt> wrote:
>>> Is it really true that there is no simple way to reverse the bit order
>>> of a SLV ?
>>> so I need to code a " for ... loop" or make a function with all that ???
>> Here is my function I use very long time:
>> function Reverse (x : std_logic_vector) return std_logic_vector is
>> alias alx : std_logic_vector (x'length - 1 downto 0) is x;
>> variable y : std_logic_vector (alx'range);
>> begin
>> for i in alx'range loop
>> y(i) := alx (alx'left - i);
>> end loop;
>> return y;
>> end;
> Andrew,
> Excellent. Thanks.
> I see there is no easy/built-in way
> but the function you just gave fits just perfect.
> lc
Or just use an alias
alias arev : std_logic_vector (a'reverse_range) is a;
regards
Alan
P.S. Just noticed that there's an alias in that function anyway - Doh!
Currently the language does not have a reverse operator because no one has bothered to submit a use case for one. If you have something that this is useful for, you should submit it to the working group.
> Currently the language does not have a reverse operator because no one has bothered to submit a use case for one.
> If you have something that this is useful for, you should submit it to the working group.
> Best Regards,
> Jim Lewis
Oh Yes... All output addresses of FFT are bit reversed and some other FFT like
variations on filters and other DSP stuff.
But this might be so specific that probably does not make a strong enough
case for adding it.
On Wednesday, October 31, 2012 4:17:49 PM UTC-5, Jim Lewis wrote:
> Currently the language does not have a reverse operator because no one has bothered to submit a use case for one. If you have something that this is useful for, you should submit it to the working group. Best Regards, Jim Lewis
Rather than adding a new operator to VHDL that adds bloat and impacts tool vendors, it would be better to add reverse() functions to the ieee packages for the standard vector types? Note that these packages are governed by the same working group. Until that time, you can write and use your own functions, with the tools you already have.
VHDL already allows extension through code to cover the need. For a taste of what can be done through "extend VHDL through code", take a look at the fixed- and floating-point packages (now part of the standard), or better yet the new Open Source VHDL Verification Methodology (OSVVM) library. These were all accomplished without changing the language itself.
> On Wednesday, October 31, 2012 4:17:49 PM UTC-5, Jim Lewis wrote:
>> Currently the language does not have a reverse operator because no one has bothered to submit a use case for one. If you have something that this is useful for, you should submit it to the working group. Best Regards, Jim Lewis
> Rather than adding a new operator to VHDL that adds bloat and impacts tool vendors, it would be better to add reverse() functions to the ieee packages for the standard vector types? Note that these packages are governed by the same working group. Until that time, you can write and use your own functions, with the tools you already have.
> VHDL already allows extension through code to cover the need. For a taste of what can be done through "extend VHDL through code", take a look at the fixed- and floating-point packages (now part of the standard), or better yet the new Open Source VHDL Verification Methodology (OSVVM) library. These were all accomplished without changing the language itself.
> Andy
You just beat me too it, I was planning to write exactly the same point (something I have also mentioned on the steering group), if it can be implemented in a package then that should be the preferred way as updating the language itself is a real struggle (there is very little money to be made in enhancing VHDL hence Vendors are reluctant to go that way, this is not my point of view).
Jim's OS-VVM is a great example of a successful package and the osvvm.org website could be a good place (even though it is owned by Aldec) to put all those great functions people write. I would not go for IEEE as the adoption process will be slow and apparently it creates lots of issues with maintenance.
