Description:
Discussing Verilog and PLI.
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New to verilog, some questions on standard libraries
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Hi, Being relatively new to verilog, still learning etc. Experienced mainly with C /C++ and micro development etc. and analogue & RF design etc. My question relates mainly to the "library" support provided with verilog & similar languages ? Is the concept commonly used features/functions/devices pooled all in one or multiple libraries available in verilog ?... more »
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How to use a Ram.
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Hi everyone. I'm trying to use a block RAM, generated by Xilinx Core Generator, but I'm not very expert in Verilog language... What I want to do is the following: - create a RAM: the ram has 8192 position (so, 13-bit address) and every position can store 49 bit (done). - on one FPGA pin, I have the incoming _serial_ data: at every... more »
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Difficulty with ALDEC Evite Verilog learning tool
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Hello I am a beginner in Verilog and have downloaded Evita Verilog interactive learning tool from ALDEC. However, when I try to run it (after its download and unzip) a window 'Select a file' pops up but there are no files in the directory. Unfortunately there is no Help file either. So I just cannot fugure out what to do.... more »
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ModelSim Synchronizer
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Hi, I have a clock signal coming into my FPGA. It is a slow clock (10kHz) that drives a state machine. I want to bring it into another clock domain by using a 3 flops in a row like shift register. The clock driving the sync flops is much faster (90MHz). I am actually running a gate level simulation (Altera Cyclone 3).... more »
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Sending SPI-style serial data to DAC on register change
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Hello-- I've designed a custom circuit board with a Cyclone II FPGA, and I am now writing Verilog code to send a control word to a 16-bit DAC. The DAC is a Texas Instruments/Burr-Brown part (DAC8580, datasheet available at [link]) which communicates via an SPI-style interface with the chip-select line (FSYNC) active high. A... more »
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newbie: help with synchronisation
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Hello there, I am new to verilog and just starting with some examples. Now I am trying to interface microcontroller to cpld chip. uC runs faster than cpld chip and I am using 8 bits wide parallel data connection. CPLD chip reads data on cpld inputs on rising clock edge. The problem for me is how to know that CPLD got the data I made available on uC... more »
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Newbie: Help with Arrays
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Hello, I'm hoping someone can help me with my problem. I'm still new with Verilog/SystemVerilog so please forgive me for this question. I have three inputs that I would like to put in an array and then use the array to compare to some constant. I have some code below, please let me know how I could do this better.... more »
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TimingAnalyzer -- Build Timing Diagrams directly from VHDL or Verilog
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Hi All, The latest version of the program is beta version 0.945. Python scripting, improved GUI zooming, and logic function simulations have been the focus in the 0.94X series An application note on the website shows how to automatically generate timing diagrams directly from vhdl. Using file I/O from VHDL or any... more »
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Passing V2K, SV attributes
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Here is another frustrating missing feature in V2K and SV. I have a dilemma and it relates to the way attributes are defined in Verilog 200x and SystemVerilog. Basically I would like to attach an attribute to a declaration inside a module. The attribute could vary from instance to instance. I thought I use macro defines, but couldn't... more »
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Weird warnings
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Hello, I've been woking on getting the LCD on my Spartan 3E Starter Kit board to work without the use of PicoBlaze. I've managed to get an init sequence, but I cannot get a write or read working. I get lots of warnings. the files are here in the second state machine is where the warnings come up: [link]... more »
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