Description:
Discussing Verilog and PLI.
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parallel CRC and ragged words
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I've been looking over the following post concerning parallel crc
computation and how to handle a multi-byte parallel bus where the data
can end in any 8b position:
[link]
All of the identities Allan calls out make perfect sense, except when... more »
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SystemVerilog functions: LRM query
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Greetings,
I'm want to call a function from another function. Both functions are
void and have inout arguments. VCS doesn't seem to complain, however
Quartus balks saying that "functions can't enable tasks" (the code is
synthesisable).
Referring back to the LRM doesn't leave me wiser as to whether Quartus... more »
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What type of shift does << represent ??
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Could some Verilog guru please clarify this a
bit ? What type of shift does << represent ?
Is it a circular shift (pushed out bits re-inserted
at the other end) or ordinary shift (pushed out
bits replaced by zeros ? Any hints, suggestions
would be helpful. Thanks in advance for your
help.
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Another syntax question
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Please pardon me if this is a very stupid question. My Verilog
is rusty. Could some Verilog guru please explain what the
following means ? I have seen it before, and it seems very
complicated. Does it mean that if sum[25] == true, normalshift is
assigned 0, and so on down the chain.
Thanks for your help.... more »
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A syntax question
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Maybe this is a very stupid question, as my Verilog is slightly rusty.
What does "aways @*" mean, does it mean that the 'always' block should
respond to any change in any input ?
A little clarification would be very helpful. Thanks in advance.
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PhD Positions at ETH Zurich
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PhD Positions at ETH Zurich
The Chair of Programming Methodology is recruiting PhD students to do
research in the following areas:
• Static program analysis, especially abstract interpretation for
mobile TouchDevelop applications
• Verification of concurrent programs, especially Scala programs... more »
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Mobile Applications Conference Bangalore on 15-October
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Hi,
I got to know of an exciting event happening in Bangalore on Jan
21st.
I guess Mobile World India 2012 comes with the exciting keynote
sessions on ‘How Operators will meet the Future Traffic Demand’, ‘What
Makes a mobile application successful’ and ‘The Future of Mobile
Technology .... more »
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Wanted data book collection
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We are developing a Verilog model for an "ancient" controller. It
contains a number of mystery IC's. We are looking at consulting or
buying a collection of databooks so that in the future this would be
easier.
Contrary to the myths out there, 90+% of databooks are not online.
Thank you!... more »
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Accessing a structure member after a cast
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Greetings,
Is there a legal way to access a member of a structure after a cast?
For example, given the structure:
<code>
typedef struct packed {
logic [7:0] byte_member;
logic flag_member;
} my_struct_t;
my_struct_t mystruct;
logic [$bits(my_struct_t)-1:0] mybits;... more »
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