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Description: Discussing Verilog and PLI.
 

doubt regarding pli simulation 
  is it possible to compile and simulate pli of verilog programs in modelsim student edition ?? if yes please send me the procedure how to compile and simulate the program in modelsim ?? the procedure is explained in [link]. but i am unbable to run it. thanks and regards bhanu
By ybhanu020@gmail.com  - Jan 5 - 1 new of 1 message    

Algorithmic state machine chart editors - do they exist ?!? 
  Hi, I've tried searching on google for ASM chart editors (freeware prefereably) to no avail ... Just doesn't seem to exist. One commercial version flowHDL® is probably out of the scope but this is not availabale as a demo version as far as I know ?!? (although it is possible to obtain for educational... more »
By asparnique  - Jan 2 - 9 new of 9 messages    

How do I control pulse width for frequency divider 
  Could some Verilog guru please help ? I have a simple divide-by-2 clock divider as: always @ (posedge clock) begin if(divby2count == 2) begin divby2count <= 0; divby2 <= 1; end else begin divby2count <= divby2count + 1; divby2 <= 0;... more »
By Daku  - Jan 2 - 2 new of 2 messages    

International Journal of Electronics, Information and Systems (IJEIS) Call for Paper 
  International Journal of Electronics, Information and Systems (IJEIS) Call for Paper The International Journal of Electronics, Information and Systems (IJEIS) publish original papers on all subjects relevant to electronics, computer science, communication network, and information systems. The highest priority will be given to those contributions... more »
By ijeiseditor  - Dec 31 2009 - 1 new of 1 message    

Multipliers, dividers, adders etc.... 
  Hi, Generally as nwbie with verilog, after sifting through a few relevant sites I couldn't help noticing requests/aid/help on various implementations of multipliers, dividers, look-ahead-carry adders .. and generally such things that are widely used & necessary. However verilog does provide *, /, +, -... more »
By asparnique  - Dec 30 2009 - 4 new of 4 messages    

Generating PWM signals for testing ? 
  Hi, I was wondering if there is a way to generate PWM signals for testing verilog code ? More so if there is a way to use as test signals, digitized PWM signals as input signals for testing/simulating verilog code, such as using a data file which represents a real PWM signal for instance ?? Cheers,... more »
By asparnique  - Dec 30 2009 - 5 new of 5 messages    

Global Warming and what you can do to against it 
  Dear All, As you know global warming is endangering the future of life on the planet. It will also affect us; rising sea levels, dwindling water supplies, mass deaths due to heat waves, stoppage of the gulfstream, which brings milder climate to north of Europe, super hurricanes, less food due to droughts are some of the effects.... more »
By ..  - Dec 29 2009 - 1 new of 1 message    

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By brandtrade  - Dec 28 2009 - 1 new of 1 message    

Requesting help on writing SV assertions 
  Hi All, I am writing assertions for one of the following scenarios. ______ ______ ______ ______ clk | | | | | | | | |______| |______| |______| |______| _____________ en | |... more »
By Veeresh  - Dec 28 2009 - 5 new of 5 messages    

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