Description:
Discussing Verilog and PLI.
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generate/genvar, for loop and procdural (always/initial) block
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Dear Community, I'm fairly new to Verilog and I'm already hitting some hurdles using the 'genvar' statement. I have written 2 verilog modules, both of them are using for loops. though the for loop index is required to be genvar when used out of always/initial block. This is my example: 1. The loop index is genvar, the compile fails otherwise:... more »
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Clock dividers and #1 delays.
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Hello Folks, I am having some trouble understanding the operation of verilog simulators w.r.t the design I want to implement below. (I have drawn the diagram such that this should look ok with a fixed width font - can't verify it looks correct using google group - but basically it is a set of two flops where the first flop has a counter... more »
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Synthesis related question - Please Help
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Maybe this is inappropriate fro this group, I have a synthesis related question. I am using Icarus Verilog 0.9.1 and I can synthesize my design, resulting in a EDIF file. My question is what would be a good tool that I can use for subsequent performance analysis. Of course, I do not have access to any commercial tool.... more »
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Conversion to RTL
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Hi, I was wonderring what this template of SystemC code would be, if written in RTL for Synthesis: ********* Code Snippet 1 *********** if (condition 1 == true) { rd_ptr++; status = "001"; ...else { wait(); ...*************************** ****** ********* Code Snippet 2 *********** if (condition 1 == true) {... more »
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timescale resolution - propagation across module boundary
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Hi, I have a simple (experimental) design consisting of testbench and DUT. The timescale compiler directive in the testbench is 1ns / 1fs, while that in the DUT is 1ns / 1ps. My prior understanding of the rules concerning timescale resolution was that the finest resolution set in any module is applied to all... more »
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vhdl range in verilog
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Hi, how do I use a vhdl range type into a verilog vector? eg. vhdl: type InputRange is ( line01, line02, line03, ... ); and then in verilog I want to use it like this: wire [32:0] In_s; assign In_s[line03] = other_signal; Is it possible? thanks ivan
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Assigning values to concatenated registers
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Could some Verilog guru please help. I am having trouble assigning values to component registers of a concatened register: I have: parameter MAX = 50; parameter DATA_WIDTH = 24; reg [7 : 0] src; reg [7 : 0] dst; reg [7 : 0] pri; reg [7 : 0] srcchk; reg [7 : 0] dstchk; reg [7 : 0] prichk; reg [7 : 0] testpri;... more »
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SystemVerilog -- pros and cons
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Hello all, I teach a class where the students spend some 200 hours coding a large project in Verilog. We do simulation and synthesis (using design compiler) but don't do layout etc. I've got a group of students asking to use SystemVerilog. My questions: - This looks like more of an upgrade (like Verilog 2001/2005) then a... more »
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sscanf issues
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Hi all, I have two questions related to the $sscanf function. First, I read input stimuli (among others) from a file. If 5 bit values are read, I should do one thing, and if only 4 bit values are read, something else should be done. E.g. while (!$feof(fd)) begin r = $fgets(textline,fd); if ($sscanf(textline, "%1b %1b %1b %1b %1b... more »
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