Daku <
daku...@gmail.com> wrote:
> Please pardon me if this is a very stupid question. My Verilog
> is rusty. Could some Verilog guru please explain what the
> following means ? I have seen it before, and it seems very
> complicated. Does it mean that if sum[25] == true, normalshift is
> assigned 0, and so on down the chain.
> Thanks for your help.
> assign normalshift =
> sum[25] ? 0 :
> sum[24] ? 1 :
> sum[23] ? 2 :
(snip)
This is the conditional operator that came from C. (At least that
is where I first knew it in this form.)
So, yes, if sum[25] is true the value is zero (the left side of the : ),
otherwise it has the value of the expression on the right side of the :.
Whether that is a good way to implement a priority encoder, I don't
know.
The logic, as written, would be very slow, propagating all the way
through in the low sum[], high return value cases. The tools are very
good at optimizing much logic, and reasonably likely this one, too.
Even so, I probably wouldn't write it this way.
-- glen