Modelling local bus IO-system

[Harald Skoglund]

I'm working on a project trying to hook a xilinx virtex-ii up to the
local bus (not pci bus) on a PLX-9656 RDK kit (PCI development board).

I'm having problems finding a way to sensibly model the bus interface,
it's a bidirectional bus with address/data multiplexed.

I have ended up with:

** Loads of stuff omitted here **

input CS, // Chip Select
inout [31:0] LAD // Address/Data
..
wire [31:0] LAD_OE;
wire [31:0] LAD_OUT;
wire [31:0] LAD_IN = LAD[31:0];
...
bufif1 IO_buf00 (LAD[00],LAD_OUT[00], LAD_OE[00]);
...
bufif1 IO_buf31 (LAD[31],LAD_OUT[31], LAD_OE[31]);

just to give a snippet of the important stuff, and that's well and good
for modelling outgoing data, but i guess i should have a way to hold the
LAD at Hi-Z whenever CS is not asserted, and i'm not sure how to
do that in a sane way.

Any help would be greatly appreciated.

--
Harald

[Petter Gustad]

Harald Skoglund <har...@NOheSPktaAM.org> writes:

> I'm working on a project trying to hook a xilinx virtex-ii up to the
> local bus (not pci bus) on a PLX-9656 RDK kit (PCI development board).
>
> I'm having problems finding a way to sensibly model the bus interface,
> it's a bidirectional bus with address/data multiplexed.
>
> I have ended up with:
>
> ** Loads of stuff omitted here **
>
> input CS, // Chip Select
> inout [31:0] LAD // Address/Data

> ...

> wire [31:0] LAD_OE;
> wire [31:0] LAD_OUT;
> wire [31:0] LAD_IN = LAD[31:0];

> ....

> bufif1 IO_buf00 (LAD[00],LAD_OUT[00], LAD_OE[00]);

> ....

> bufif1 IO_buf31 (LAD[31],LAD_OUT[31], LAD_OE[31]);
>
> just to give a snippet of the important stuff, and that's well and good
> for modelling outgoing data, but i guess i should have a way to hold the
> LAD at Hi-Z whenever CS is not asserted, and i'm not sure how to
> do that in a sane way.

wire [31:0] LAD_OE = {32{CS}};

assuming CS is active high.

Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter