Verilog to VHDL conversion

[johnp]

I need to convert some Verilog files to VHDL and have looked at
assorted (free) tools. So far,
the Verilog2VHDL tool from Questa Technologies looks promising, but it
has a number of bugs.

Does anyone know if they still exist and are supporting the tool?

Can anyone suggest a better tool?

Thanks!

John Providenza

[Stephen Williams]

Icarus Verilog has a VHDL target code generator that is being
actively maintained.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

[Cary R.]

On 9/2/2011 8:17 PM, Stephen Williams wrote:
> On 09/01/2011 07:22 AM, johnp wrote:
>> I need to convert some Verilog files to VHDL and have looked at
>> assorted (free) tools. So far,
>> the Verilog2VHDL tool from Questa Technologies looks promising, but it
>> has a number of bugs.
>>
>> Does anyone know if they still exist and are supporting the tool?
>>
>> Can anyone suggest a better tool?
>
> Icarus Verilog has a VHDL target code generator that is being
> actively maintained.
>

Note that the Icarus VHDL target was designed for translating
synthesizable Verilog code. It is not currently and may never be a
general purpose Verilog to VHDL converter.

Cary

[johnp]

I've looked at Icarus and it's VHDL translation doesn't quite fit the
bill. The Questa Technologies folks
have emailed back and look to be making updates and bug-fixes. We'll
see how they work out!

John P.

[anki...@gmail.com]

In VHDL 2008, new feature 'Hierarchical Names' was introduced, but I couldn't find an example of how to implement these Hierarchical Names in VHDL code. Even the Doulus website is not explaining it properly. Can anybody guide me on this?
You can send me email to anki...@gmail.com too.

Thank you.

[Nikolaos Kavvadias]

Hi all,

I didn't know about the Questa tool. At some point (I think this tool is still available) X-Tek Corp had an interesting Verilog<->VHDL translator. It is not a free tool though, not sure if you can get an evaluation version.

BTW using the Icarus target feature (Verilog->VHDL only) looks interested.

Does anyone use this feature? What are essentially the capabilities of this target? It would be interesting if it can get basic synthesizable Verilog to VHDL correctly.

Best,
Nikos Kavvadias

[Cary R.]

On 9/17/2013 4:07 AM, Nikolaos Kavvadias wrote:

> BTW using the Icarus target feature (Verilog->VHDL only) looks
> interested.
>
> Does anyone use this feature? What are essentially the capabilities
> of this target? It would be interesting if it can get basic
> synthesizable Verilog to VHDL correctly.

The Icarus VHDL code generator was a GSOC project from a few years ago
and has had only minimal support since then. It is described on the
following web page:

http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator

Since it's free it's easy to see if it works for you. Unfortunately if
it doesn't support what you need there may not be resources available to
enhance it, but bug reports or discussions on the Icarus development
mailing list are always welcomed. At the moment the project is focusing
on fixing bugs in existing functionality, adding SystemVerilog support
and reading VHDL RTL to allow mixed language simulations.

Cary

[amal.kh...@gmail.com]

Here is the new web site:

http://www.edautils.com

-- Amal

[alluupe...@gmail.com]

There is a program called vhdl2v that converts VHDL vode to verilog code.

the program is free, you can download it from this link
http://www.ocean-logic.com/downloads.htm

this tool is not perfect, but give it a try.

[Ravali Thangellapalli]

can anyone help me can anyone sugguest vdhl into verilog converter
Thanks..

[tcj9...@gmail.com]

Yes, I was going to suggest this. It is quite good compared to the technology about a decade ago. And it's free!

Because it is free it is not perfect, as alley-oop said. It works best with code that is written in a Verilog-style without much VHDL abstraction. You'll have to do some hand-edit fix-ups and may have to tweak the VHDL code to get it through. Most of the errors in Verilog output result in syntax errors - so they'll be easy to find.

Good luck.