<OT> ModelSim Help <OT>

[KellyB]

Hi,

I'm new to testbenches so I set a goal to get those Verilog examples
to work under ModelSim PE Student Edition 6.4.

I'm trying to do the simplest of things - to run the counter.v and
tcounter.v simulation and create a waveform. However once compiled, I
have no objects hence nothing that can be added to the waveform.

I get no errors at all, just no objects after I compile. I see the two
files under my library, I can click on the testbench file and it opens
in SIM but objects window is simply empty.

Please Help !!!

[Kevin Neilson]

Did you "link" the design using the "vsim" command? There are three
basic steps: compile ("vlog"), link ("vsim"), and run ("run"). -Kevin

[KellyB]

Hi,
Thanks for the reply.

Ive managed to obtain the compiled entities after a bit of tinkering.
But now i have a different problem.I cannot simulate :(

This is the code:

module stimcrct;
reg A,B,C;
wire x,y;
circuit_with_delay cwd(A,B,C,x,y);
initial
begin
A = 1'b0 ; B = 1'b0 ; C = 1'b0;
#100
A = 1'b1 ; B = 1'b1 ; C = 1'b1;
#100 $finish;
end
endmodule

module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule

This is what i get :

# Compile of test.v was successful.
vsim work.circuit_with_delay
# vsim work.circuit_with_delay
# Error loading design
vsim work.stimcrct
# vsim work.stimcrct
# Error loading design

I am obviously missing something really silly.BTW this is the first time
that I am using ModelSim and I have only just started to learn verilog.

Best Regards

[KellyB]

KellyB wrote:
> Kevin Neilson wrote:
>> KellyB wrote:
>>> Hi,
>>>
>>> I'm new to testbenches so I set a goal to get those Verilog examples
>>> to work under ModelSim PE Student Edition 6.4.
>>>
>>> I'm trying to do the simplest of things - to run the counter.v and
>>> tcounter.v simulation and create a waveform. However once compiled, I
>>> have no objects hence nothing that can be added to the waveform.

..snip..

I tried simulating the *new* code instead (The one posted above) , after
the initial failure with the counter.v and tcounter.v codes Hope this
does not create any confusion.

Thanks

[Kevin Neilson]

I don't know what might be wrong. It was successful for me. I put the
code in two files and compiled:

VSIM> vlog hdl/circuit_with_delay.v
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module circuit_with_delay
#
# Top level modules:
# circuit_with_delay
VSIM> vlog hdl/stimcrct.v
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module stimcrct
#
# Top level modules:
# stimcrct
VSIM> vsim stimcrct
# vsim stimcrct
# Loading
c:\xilinx\ISE\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll
# Loading work.stimcrct(fast)
# Loading work.circuit_with_delay(fast)

This assumes there is already a library called 'work'. I put the files
in a folder called "hdl". Note: it's good design practice to put each
module in its own file and make the filename the same as the module
name. -Kevin

[KellyB]

Thanks for the reply Kevin.I got the manuals from the website and
finally managed to run the code. There was some issue with user
privileges on my system (Windows vista) .
Its working as it should be.

Thanks Again