clock divider
rekz
// Generate a 1 kHz clock from 50 MHz clock
module LCDClkDiv(Clk, Rst, ClkOut);
input Clk, Rst;
output reg ClkOut;
parameter DivVal = 1250;
reg[24:0] DivCnt;
reg ClkInt;
always @(posedge Clk) begin
if( Rst == 1 )begin
DivCnt <= 0;
ClkOut <= 0;
ClkInt <= 0;
end
else begin
if( DivCnt == (DivVal-1) ) begin
ClkOut <= ~ClkInt;
ClkInt <= ~ClkInt;
DivCnt <= 0;
end
else begin
ClkOut <= ClkInt;
ClkInt <= ClkInt;
DivCnt <= DivCnt + 1;
end
end
end
endmodule
However I don't understand the calculation on how it can convert from
a 50MHz to a 1kHz above... what are the calculations? The 50MHz comes
from the FPGA clock
John_H
This will actually produce a 2 kHz output clock from a 50 MHz input.
If you read through the code and follow along, you'll see the DivCnt
will count from 0 to 1249, inclusive. Every time it hits the terminal
count, the output clock *toggles* so a full period is two toggles or
2500 counts.
(Also, DivCnt only needs to be 11 bits in this configuration, 12 bits
for the 1 kHz output.)
gabor
Umm... I though 50,000,000 divided by 2,500
would be 20,000 not 2,000?
gabor
Any chance the real value of DivVal has been set
to 50,000 using defparam at the instantiation?
rekz
No the real value of DivVal hasn't been set to 50,000... it's 50MHz
directly from the FPGA
rekz
I guess you're right the comments are misleading it should be 20MHz
Muzaffer Kal
wrote:
>> > > > > I have the following clock divider
>>
>> > > > > // Generate a 1 kHz clock from 50 MHz clock
>> > > > > module LCDClkDiv(Clk, Rst, ClkOut);
>>
>> > > > > input Clk, Rst;
>> > > > > output reg ClkOut;
>>
>> > > > > parameter DivVal = 1250;
>> No the real value of DivVal hasn't been set to 50,000... it's 50MHz
>> directly from the FPGA
>
>I guess you're right the comments are misleading it should be 20MHz
>clock from a 50 MHz
It's 20 KHz, not 20 MHz and it's still possible that when LCDCLKDiv is
instantiated the value of DivVal can be overrideen. Check where it is
used.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
rekz
> On Sun, 18 Apr 2010 18:42:03 -0700 (PDT), rekz <aditya15...@gmail.com>
what if I want the equivalent of:
always begin
Clk <= 1;
#100;
Clk <= 0;
#100;
end
using the code above?
David Rogoff
Just replace the # delays with a counter that counts the correct number
of your faster clock to add up to that delay!
Come on people - think or read a book or do some google searches
instead of asking these really simple questions and expecting other
people to take their valuable time to answer them. This is something
you learn in the first couple of days of writing RTL.
In addition, it points out that a lot of the people asking questions
wouldn't know an AND gate if it hit him in the head since questions
like this show that the person asking it has no idea how to do digital
design and thinks that Verilog will magically turn him into a hardware
designer.
It's like thinking that knowing how to use all the features in
Microsoft Word means you know how to write a novel.
RULE 1: if you can't draw at least a rough schematic, using d
flip-flops and AND/OR/NOR gates, of the crcuit you are trying to code
in Verilog then you shouldn't be trying. You need to go back and
understand digital design and then learn how to use an HDL to implement
it.
more rules to follow...