SV-201x Listening Campaign
Shalom Bresticker
time to start thinking about ongoing development of the language. The
standardization committees will soon begin work on a new revision, and
Brad Pierce is spearheading an effort to listen to the views of the
user community on what should be fixed, changed or added. Please see
his blog post at http://bradpierce.wordpress.com/2009/12/14/systemverilog-201x-listening-campaign/
and make your views known!
Shalom
gabor
wrote:
> and make your views known!
>
> Shalom
I'm still using Verilog 2001. Do newer versions have
enumerated types?
Regards,
Gabor
Jonathan Bromley
Now that SystemVerilog-2009 has been standardized and
published
[Gabor]
I'm still using Verilog 2001. Do newer versions have
enumerated types?
Yes, although the mechanics are closer to C++ enums than to
VHDL: a SystemVerilog enum is based on an integral type of
your choice, and the numeric values of its enumeration
literals are under your control. There are sensible
defaults so that you don't have to specify that stuff
unless the details are important to you.
Enums will work out-of-the-box in all the major simulators
and synthesis tools; a recent thread on comp.arch.fpga
showed just how much support already exists for SV
even in the Altera Edition of Modelsim, for example.
(Thread titled "SystemVerilog Verification Example
using Quartus and ModelSim").
For most users, the gaping hole in SystemVerilog support
is Xilinx; neither XST nor ISIM had any useul support
the last time I looked. Quartus, Synplify, Precision
and Synopsys DC all have excellent support for the
synthesis subset of SV.
There's much more than enums.
In the world of data types SV has structs, unions, better
facilities for manipulation of arrays, 2-state data types
(int etc.), facilities for writing constant and aggregate
values of the new types, and a nice distinction between
packed and unpacked aggregates that matches RTL needs well.
Packages, loosely similar to the VHDL construct of the
same name, allow you to manage all your custom declarations
in a convenient way and share them across your design.
For RTL there is a mass of minor but significant
improvements including a robust way to express what has
traditionally been done with parallel_case pragmas, and
some very nifty shorthand syntax for port connections.
The interface construct allows you to gather a bundle of
wiring (such as a microprocessor bus) into one definition,
and then instantiate it as many times as you need in your
design and connect a module's port to one of those instances.
Finally there is a big collection of convenience features,
improvements and cleanups for design; in particular, changes
in the way continuous assign works, so that you almost never
need to declare a "wire" anywhere in an RTL design now.
And that's just the synthesisable RTL stuff!
For testbenches, so many things..... and, as was pointed out
on the comp.arch.fpga thread I mentioned, most of those
things work today in standard simulators if you enable
SystemVerilog compilation; there are just two big areas
(assertions and randomization) that require high-cost
simulator features.
--
Jonathan Bromley
Shalom Bresticker
assertions.
That is, if you have property or sequence declarations inlined in your
code, the compilation fails.
That means you have to enclose them in `ifdefs or translate_off
directives, which is very painful when you want to compile external
IP.
Ouch!
Shalom
On Jan 17, 1:24 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
Petter Gustad
> is Xilinx; neither XST nor ISIM had any useul support
> the last time I looked. Quartus, Synplify, Precision
> and Synopsys DC all have excellent support for the
> synthesis subset of SV.
A design I worked on a couple years ago was using SV. Unfortunately
the back-end ASIC tools got confused by the use of interfaces. This
was quite odd as I expected them not to be visible after synthesis (DC
in this case). Well, hopefully things have improved over the last few
years.
Petter
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