AES decrytion =>ASIC

[swissi...@gmail.com]

Hey folks , i need ur opinion about something :
To implement an AES 256 decryption (CBC mode ) algorithm in ASIC ,
what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :

* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
* Full outerround pipelining
* Inner-round pipelining
* Partial mixed innerand outerroundpipelining
* Full mixed inner- and outer-round pipelining
* other ...

[d_s_...@yahoo.com]

First you have to define "best". Lowest gate count? Lowest Si cost?
Highest clock rate? Highest throughput? Lowest latency? Easiest to
test? Shortest development time? Fewest copyright infringements?

It isn't that tough to mock up a few versions and try them. Then work
on what "best" means.