`default_nettype none scope

[gabor]

I'm trying to debug a project I inherited that is littered with port
size
mismatches and other issues, many created by implicit wire
declarations.

So I added a line
`default_nettype none

to help find the issues. Of course this breaks my Verilog 2001 style
port declarations. So I thought, great I'll move the line with
`default_nettype none down below the port declarations so it
just checks in the body of the code. Unfortunately, unlike `define,
the scope of `default_nettype seems to cover the entire file
regardless
of its placement within the file.

Furthermore when compiling the entire project, the `default_nettype
scope covers other modules as well. Is there any way to selectively
turn this on and off? Or should I give up and comment it out after
I finish debugging one module?

Frustrated,
Gabor

[Mark Curry]

In article <01015b95-e2cb-43c4...@8g2000vbg.googlegroups.com>,

I can answer the second question - we started using the
`default_nettype none directive a few years ago. Like you,
we ran into problems with old code that depended on the
implicit wires would break, depending on compilation ordering
(because the directive is sticky). So those of us that
wanted the directive added it to the top of the file (module),
and then at the end of the module turned it back off with:
`default_nettype wire

So now our new module template is almost always:
`default_nettype none
module blah();
...
endmodule
`default_nettype wire

I've never played with it WITHIN a module as you're doing, so
can't help much there.

Regards,

Mark

[gabor]

On Jun 11, 4:47 pm, gtw...@sonic.net (Mark Curry) wrote:
> In article <01015b95-e2cb-43c4-b185-374130d2d...@8g2000vbg.googlegroups.com>,

Thanks, I'll give that a shot. When I saw that the placement inside
the module had the same effect as placement at the top of the file,
I assumed that adding another `default_nettype directive after the
endmodule would be pointless. Behavior when placed inside the
module may be synthesizer specific. I'm using Xilinx XST 12.1
at the moment. I didn't look at this too deeply, but in the
Doulos "Golden Reference" guide it says that the effect of compiler
directives starts from the place where it appears in the source
code. This is certainly true of `define.

I actually didn't mind fixing all of the other modules in this
particular design, but I don't like the idea of reworking
purchased IP, some of which is delivered as source. Your
method seems safe (if it works) for adding modules to an
existing design.

Thanks for the tip,

Gabor

[sh...@cadence.com]

On Jun 11, 4:02 pm, gabor <ga...@alacron.com> wrote:
>
> So I thought, great I'll move the line with
> `default_nettype none down below the port declarations so it
> just checks in the body of the code.  Unfortunately, unlike `define,
> the scope of `default_nettype seems to cover the entire file
> regardless
> of its placement within the file.

The LRM specifies that `default_nettype can only be used outside of
module declarations. The intent is apparently that it applies to all
of a module or none of it. There is some logic to this, since there
are cases where you cannot know whether you have an implicit net until
you have reached the end of the module and not found a net declaration
corresponding to a port declaration. It could be hiding at the very
end of the module, after all of the uses. Was that missing net
declaration missing before or after the directive? And what if there
were multiple directives specifying different net types within the
same module? Which one would apply in those cases?

Sadly, this isn't an issue for the situation where you really wanted
to turn off the implicit declarations, where the identifier is used in
a module or primitive instantiation. There the cause of the implicit
declaration is in a clear position. It only comes up in the situation
where you didn't want to turn off the implicit declarations, when the
module port declarations are missing a matching net declaration.

But anyway, the LRM doesn't allow them inside of modules, so what you
are doing is invalid. The tools shouldn't be allowing it. If they
do, you can't really complain too much about how they treat it in that
case. If they treat it as applying to all or none of the module it is
inside, that just matches the original intent of requiring it to be
outside.

> Furthermore when compiling the entire project, the `default_nettype
> scope covers other modules as well.  Is there any way to selectively
> turn this on and off?  Or should I give up and comment it out after
> I finish debugging one module?

It will apply until you hit another directive that changes it. You
can always change the default again with another `default_nettype
directive. Or you can set all the directives back to their defaults
with `resetall.

[gabor]

I guess it makes sense that it should be outside the module.
Xilinx XST doesn't seem to care where it is placed.

>
> > Furthermore when compiling the entire project, the `default_nettype
> > scope covers other modules as well.  Is there any way to selectively
> > turn this on and off?  Or should I give up and comment it out after
> > I finish debugging one module?
>
> It will apply until you hit another directive that changes it.  You
> can always change the default again with another `default_nettype
> directive.  Or you can set all the directives back to their defaults
> with `resetall.

I'll stick with Mark's suggestion of just putting `default_nettype
back to "wire" after the end of the module. I can't rely on other
modules to have a `resetall directive at the start of the file as
suggested in the LRM. And placing a `resetall at the end of my
file may have other unintended consequences.

Regards,
Gabor